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Searched refs:BIT6 (Results 1 – 25 of 33) sorted by relevance

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/drivers/scsi/
Dtmscsim.h185 #define BIT6 0x00000040 macro
212 #define SRB_START_ BIT6 /*;arbitration+msg_out+command_out*/
240 #define DATAIN BIT6
390 #define ILLEGAL_OP_ERR BIT6
399 #define INVALID_CMD BIT6
423 #define DIS_INT_ON_SCSI_RST BIT6
428 #define EN_FEATURE BIT6
433 #define EN_QTAG_MSG BIT6
441 #define EATER_35NS BIT6
442 #define EATER_0NS (BIT7+BIT6)
[all …]
Ddc395x.h69 #define BIT6 0x00000040 macro
137 #define DATAIN BIT6
179 #define EN_ATN_STOP BIT6
/drivers/staging/vt6655/
D80211hdr.h44 #define BIT6 0x00000040 macro
166 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n) >> 8) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
188 #define WLAN_GET_CAP_INFO_PBCC(n) ((((n) >> 8) & BIT6) >> 6)
201 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n)) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
224 #define WLAN_GET_CAP_INFO_PBCC(n) (((n) & BIT6) >> 6)
Dhostap.h42 #define WLAN_RATE_12M BIT6
/drivers/staging/vt6656/
D80211hdr.h42 #define BIT6 0x00000040 macro
163 & (BIT4|BIT5|BIT6|BIT7)) >> 4)
185 #define WLAN_GET_CAP_INFO_PBCC(n) ((((n) >> 8) & BIT6) >> 6)
197 #define WLAN_GET_FC_FSTYPE(n) ((((WORD)(n)) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
218 #define WLAN_GET_CAP_INFO_PBCC(n) (((n) & BIT6) >> 6)
Dhostap.h42 #define WLAN_RATE_12M BIT6
/drivers/video/via/
Dlcd.c390 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6); in load_lcd_scaling()
625 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
634 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
647 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6); in integrated_lvds_disable()
653 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
677 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
686 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
702 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6); in integrated_lvds_enable()
708 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
Ddvi.c69 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
76 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
435 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0); in viafb_dvi_enable()
Dhw.c1684 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); in viafb_init_dac()
1691 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); in viafb_init_dac()
1695 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); in viafb_init_dac()
2048 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in enable_second_display_channel()
2050 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in enable_second_display_channel()
2056 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in disable_second_display_channel()
2058 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in disable_second_display_channel()
Dshare.h34 #define BIT6 0x40 macro
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h236 #define IMR_MGNTDOK BIT6
251 #define TPPoll_MQ BIT6
291 #define AcmHw_VoqStatus BIT6
381 #define RRSR_12M BIT6
/drivers/staging/keucr/
Dsmilecc.c42 #define BIT6 0x40 macro
110 if ((a&BIT6) != 0) { /* If D_all(all bit XOR) = 1 */ in calculate_ecc()
/drivers/staging/rtl8192u/
Dr8192U_hw.h235 #define AcmHw_VoqStatus BIT6
313 #define RRSR_12M BIT6
/drivers/char/pcmcia/
Dsynclink_cs.c300 #define IRQ_EXITHUNT BIT6 // receive frame start
301 #define IRQ_RXTIME BIT6 // rx char timeout
308 #define XFW BIT6 // transmit FIFO write enable
671 #define CMD_RXRESET BIT6 // receiver reset
920 if (status & (BIT7 + BIT6)) { in rx_ready_async()
934 else if (status & BIT6) in rx_ready_async()
1478 info->read_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
1480 info->ignore_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
2186 set_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
2188 clear_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
[all …]
/drivers/net/hamradio/
Dz8530.h117 #define BIT6 1 /* 6 bit/8bit sync */ macro
/drivers/tty/serial/
Dzs.h172 #define BIT6 1 /* 6 bit/8bit sync */ macro
Dip22zilog.h153 #define BIT6 1 /* 6 bit/8bit sync */ macro
Dsunzilog.h155 #define BIT6 1 /* 6 bit/8bit sync */ macro
Dpmac_zilog.h246 #define BIT6 1 /* 6 bit/8bit sync */ macro
/drivers/tty/
Dsynclinkmp.c417 #define RXINTE BIT6
423 #define IDLE BIT6
436 #define PMP BIT6
437 #define SHRT BIT6
2608 if (timerstatus0 & (BIT7 | BIT6)) in synclinkmp_interrupt()
2612 if (timerstatus1 & (BIT7 | BIT6)) in synclinkmp_interrupt()
4439 RegValue=BIT6; in async_mode()
4448 RegValue=BIT6; in async_mode()
4576 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */ in hdlc_mode()
4604 RegValue |= BIT6; in hdlc_mode()
[all …]
Dsynclink_gt.c422 #define IRQ_CTS BIT6
1425 value |= BIT6; in set_break()
1427 value &= ~BIT6; in set_break()
4012 wr_reg32(info, RDCSR, BIT6); in rx_start()
4025 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); in rx_start()
4322 val |= BIT6; in sync_mode()
4414 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ in sync_mode()
4416 val |= BIT6; /* 010, txclk = BRG */ in sync_mode()
4445 val = BIT7 + BIT6; break; in sync_mode()
4446 default: val = BIT6; // NRZ encodings in sync_mode()
[all …]
Dsynclink.c507 #define RXSTATUS_IDLE_RECEIVED BIT6
547 #define TXSTATUS_IDLE_SENT BIT6
568 #define MISCSTATUS_DCD BIT6
592 #define SICR_DCD_INACTIVE BIT6
593 #define SICR_DCD (BIT7+BIT6)
628 #define TXSTATUS_IDLE_SENT BIT6
5212 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6)); in usc_enable_loopback()
5251 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6)); in usc_enable_loopback()
5921 RegValue |= BIT6; in usc_set_async_mode()
5978 RegValue |= BIT6; in usc_set_async_mode()
[all …]
/drivers/staging/rtl8187se/
Dr8180_rtl8225z2.c903 write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5 | BIT6)))); in SetZebraRFPowerState8185()
964 (u1bTmp | BIT5 | BIT6)); in SetZebraRFPowerState8185()
1024 write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6)); in SetZebraRFPowerState8185()
Dr8180_hw.h30 #define BIT6 0x00000040 macro
/drivers/net/wan/
Dz85230.h138 #define BIT6 1 /* 6 bit/8bit sync */ macro

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