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Searched refs:CLK_CTL (Results 1 – 3 of 3) sorted by relevance

/drivers/staging/rts_pstor/
Drtsx_card.c772 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in switch_ssc_clock()
789 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0); in switch_ssc_clock()
886 RTSX_WRITE_REG(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ); in switch_normal_clock()
900 RTSX_WRITE_REG(chip, CLK_CTL, 0xFF, 0); in switch_normal_clock()
Dsd.c548 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in sd_set_sample_push_timing()
551 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_sample_push_timing()
555 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in sd_set_sample_push_timing()
558 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_sample_push_timing()
567 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in sd_set_sample_push_timing()
570 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_sample_push_timing()
906 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK); in sd_change_phase()
910 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0); in sd_change_phase()
925 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK); in sd_change_phase()
951 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0); in sd_change_phase()
Drtsx_card.h832 #define CLK_CTL 0xFC02 macro