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Searched refs:CLOCK (Results 1 – 11 of 11) sorted by relevance

/drivers/mfd/
Dasic3.c385 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), in asic3_irq_probe()
602 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); in asic3_clk_enable()
604 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); in asic3_clk_enable()
618 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); in asic3_clk_disable()
620 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); in asic3_clk_disable()
747 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), in asic3_mmc_enable()
971 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); in asic3_probe()
1031 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0); in asic3_remove()
/drivers/video/sis/
Dvstruct.h182 unsigned short CLOCK; member
187 unsigned short CLOCK; member
192 unsigned short CLOCK; member
Dinit.c1552 return(SiS_Pr->SiS_MCLKData_0[index].CLOCK); in SiS_GetMCLK()
1554 return(SiS_Pr->SiS_MCLKData_1[index - 4].CLOCK); in SiS_GetMCLK()
1556 return(SiS_Pr->SiS_MCLKData_0[index].CLOCK); in SiS_GetMCLK()
2315 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetCRT1FIFO_300()
2323 MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK; in SiS_SetCRT1FIFO_300()
2437 VCLK = SiS_Pr->SiS_VCLKData[data].CLOCK; in SiS_SetCRT1FIFO_630()
2442 MCLK16 = SiS_Pr->SiS_MCLKData_0[data].CLOCK * 16; in SiS_SetCRT1FIFO_630()
2583 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetVCLKState()
2751 data2 = SiS_Pr->SiS_VCLKData[data2].CLOCK; in SiS_SetCRT1ModeRegs()
Dinitextlfb.c88 Clock = SiS_Pr->SiS_VCLKData[ClockIndex].CLOCK * 1000; in sisfb_mode_rate_to_dclock()
Dinit301.c1438 SiS_Pr->SiS_VCLKData[VCLK_CUSTOM_315].CLOCK = in SiS_GetLCDInfoBIOS()
1439 SiS_Pr->SiS_VBVCLKData[VCLK_CUSTOM_315].CLOCK = (unsigned short)((unsigned char)ROMAddr[18]); in SiS_GetLCDInfoBIOS()
1834 SiS_Pr->SiS_VCLKData[idx].CLOCK = in SiS_GetLCDResInfo()
1835 SiS_Pr->SiS_VBVCLKData[idx].CLOCK = SiS_Pr->CP_PrefClock; in SiS_GetLCDResInfo()
5035 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetCRT2FIFO_300()
5062 MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK; in SiS_SetCRT2FIFO_300()
5125 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetCRT2FIFO_300()
10168 index = SiS_Pr->SiS_VCLKData[index].CLOCK; in SetDelayComp661()
/drivers/staging/xgifb/
Dvb_struct.h53 unsigned short CLOCK; member
204 unsigned short CLOCK; member
DXGI_main_26.c180 Clock = XGI_Pr->VCLKData[ClockIndex].CLOCK * 1000; in XGIfb_mode_rate_to_dclock()
Dvb_setmode.c1474 VCLK = pVBInfo->VCLKData[index].CLOCK; in XGI_SetVCLKState()
/drivers/usb/misc/sisusbvga/
Dsisusb_struct.h116 unsigned short CLOCK; member
Dsisusb_init.c639 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetVCLKState()
/drivers/gpu/drm/nouveau/
Dnv50_display.c784 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)); in nv50_display_unk20_handler()
798 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff; in nv50_display_unk20_handler()