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1 /*
2  * SDIO spec header file
3  * Protocol and standard (common) device definitions
4  *
5  * Copyright (C) 1999-2013, Broadcom Corporation
6  *
7  *      Unless you and Broadcom execute a separate written software license
8  * agreement governing use of this software, this software is licensed to you
9  * under the terms of the GNU General Public License version 2 (the "GPL"),
10  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
11  * following added to such license:
12  *
13  *      As a special exception, the copyright holders of this software give you
14  * permission to link this software with independent modules, and to copy and
15  * distribute the resulting executable under terms of your choice, provided that
16  * you also meet, for each linked independent module, the terms and conditions of
17  * the license of that module.  An independent module is a module which is not
18  * derived from this software.  The special exception does not apply to any
19  * modifications of the software.
20  *
21  *      Notwithstanding the above, under no circumstances may you combine this
22  * software in any way with any other Broadcom software provided under a license
23  * other than the GPL, without Broadcom's express prior written consent.
24  *
25  * $Id: sdio.h 308973 2012-01-18 04:19:34Z $
26  */
27 
28 #ifndef	_SDIO_H
29 #define	_SDIO_H
30 
31 
32 /* CCCR structure for function 0 */
33 typedef volatile struct {
34 	uint8	cccr_sdio_rev;		/* RO, cccr and sdio revision */
35 	uint8	sd_rev;			/* RO, sd spec revision */
36 	uint8	io_en;			/* I/O enable */
37 	uint8	io_rdy;			/* I/O ready reg */
38 	uint8	intr_ctl;		/* Master and per function interrupt enable control */
39 	uint8	intr_status;		/* RO, interrupt pending status */
40 	uint8	io_abort;		/* read/write abort or reset all functions */
41 	uint8	bus_inter;		/* bus interface control */
42 	uint8	capability;		/* RO, card capability */
43 
44 	uint8	cis_base_low;		/* 0x9 RO, common CIS base address, LSB */
45 	uint8	cis_base_mid;
46 	uint8	cis_base_high;		/* 0xB RO, common CIS base address, MSB */
47 
48 	/* suspend/resume registers */
49 	uint8	bus_suspend;		/* 0xC */
50 	uint8	func_select;		/* 0xD */
51 	uint8	exec_flag;		/* 0xE */
52 	uint8	ready_flag;		/* 0xF */
53 
54 	uint8	fn0_blk_size[2];	/* 0x10(LSB), 0x11(MSB) */
55 
56 	uint8	power_control;		/* 0x12 (SDIO version 1.10) */
57 
58 	uint8	speed_control;		/* 0x13 */
59 } sdio_regs_t;
60 
61 /* SDIO Device CCCR offsets */
62 #define SDIOD_CCCR_REV			0x00
63 #define SDIOD_CCCR_SDREV		0x01
64 #define SDIOD_CCCR_IOEN			0x02
65 #define SDIOD_CCCR_IORDY		0x03
66 #define SDIOD_CCCR_INTEN		0x04
67 #define SDIOD_CCCR_INTPEND		0x05
68 #define SDIOD_CCCR_IOABORT		0x06
69 #define SDIOD_CCCR_BICTRL		0x07
70 #define SDIOD_CCCR_CAPABLITIES		0x08
71 #define SDIOD_CCCR_CISPTR_0		0x09
72 #define SDIOD_CCCR_CISPTR_1		0x0A
73 #define SDIOD_CCCR_CISPTR_2		0x0B
74 #define SDIOD_CCCR_BUSSUSP		0x0C
75 #define SDIOD_CCCR_FUNCSEL		0x0D
76 #define SDIOD_CCCR_EXECFLAGS		0x0E
77 #define SDIOD_CCCR_RDYFLAGS		0x0F
78 #define SDIOD_CCCR_BLKSIZE_0		0x10
79 #define SDIOD_CCCR_BLKSIZE_1		0x11
80 #define SDIOD_CCCR_POWER_CONTROL	0x12
81 #define SDIOD_CCCR_SPEED_CONTROL	0x13
82 #define SDIOD_CCCR_UHSI_SUPPORT		0x14
83 #define SDIOD_CCCR_DRIVER_STRENGTH	0x15
84 #define SDIOD_CCCR_INTR_EXTN		0x16
85 
86 /* Broadcom extensions (corerev >= 1) */
87 #define SDIOD_CCCR_BRCM_CARDCAP			0xf0
88 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_SUPPORT	0x02
89 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_EXT	0x04
90 #define SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC	0x08
91 #define SDIOD_CCCR_BRCM_CARDCTL			0xf1
92 #define SDIOD_CCCR_BRCM_SEPINT			0xf2
93 
94 /* cccr_sdio_rev */
95 #define SDIO_REV_SDIOID_MASK	0xf0	/* SDIO spec revision number */
96 #define SDIO_REV_CCCRID_MASK	0x0f	/* CCCR format version number */
97 
98 /* sd_rev */
99 #define SD_REV_PHY_MASK		0x0f	/* SD format version number */
100 
101 /* io_en */
102 #define SDIO_FUNC_ENABLE_1	0x02	/* function 1 I/O enable */
103 #define SDIO_FUNC_ENABLE_2	0x04	/* function 2 I/O enable */
104 
105 /* io_rdys */
106 #define SDIO_FUNC_READY_1	0x02	/* function 1 I/O ready */
107 #define SDIO_FUNC_READY_2	0x04	/* function 2 I/O ready */
108 
109 /* intr_ctl */
110 #define INTR_CTL_MASTER_EN	0x1	/* interrupt enable master */
111 #define INTR_CTL_FUNC1_EN	0x2	/* interrupt enable for function 1 */
112 #define INTR_CTL_FUNC2_EN	0x4	/* interrupt enable for function 2 */
113 
114 /* intr_status */
115 #define INTR_STATUS_FUNC1	0x2	/* interrupt pending for function 1 */
116 #define INTR_STATUS_FUNC2	0x4	/* interrupt pending for function 2 */
117 
118 /* io_abort */
119 #define IO_ABORT_RESET_ALL	0x08	/* I/O card reset */
120 #define IO_ABORT_FUNC_MASK	0x07	/* abort selction: function x */
121 
122 /* bus_inter */
123 #define BUS_CARD_DETECT_DIS	0x80	/* Card Detect disable */
124 #define BUS_SPI_CONT_INTR_CAP	0x40	/* support continuous SPI interrupt */
125 #define BUS_SPI_CONT_INTR_EN	0x20	/* continuous SPI interrupt enable */
126 #define BUS_SD_DATA_WIDTH_MASK	0x03	/* bus width mask */
127 #define BUS_SD_DATA_WIDTH_4BIT	0x02	/* bus width 4-bit mode */
128 #define BUS_SD_DATA_WIDTH_1BIT	0x00	/* bus width 1-bit mode */
129 
130 /* capability */
131 #define SDIO_CAP_4BLS		0x80	/* 4-bit support for low speed card */
132 #define SDIO_CAP_LSC		0x40	/* low speed card */
133 #define SDIO_CAP_E4MI		0x20	/* enable interrupt between block of data in 4-bit mode */
134 #define SDIO_CAP_S4MI		0x10	/* support interrupt between block of data in 4-bit mode */
135 #define SDIO_CAP_SBS		0x08	/* support suspend/resume */
136 #define SDIO_CAP_SRW		0x04	/* support read wait */
137 #define SDIO_CAP_SMB		0x02	/* support multi-block transfer */
138 #define SDIO_CAP_SDC		0x01	/* Support Direct commands during multi-byte transfer */
139 
140 /* power_control */
141 #define SDIO_POWER_SMPC		0x01	/* supports master power control (RO) */
142 #define SDIO_POWER_EMPC		0x02	/* enable master power control (allow > 200mA) (RW) */
143 
144 /* speed_control (control device entry into high-speed clocking mode) */
145 #define SDIO_SPEED_SHS		0x01	/* supports high-speed [clocking] mode (RO) */
146 #define SDIO_SPEED_EHS		0x02	/* enable high-speed [clocking] mode (RW) */
147 
148 /* for setting bus speed in card: 0x13h */
149 #define SDIO_BUS_SPEED_UHSISEL_M	BITFIELD_MASK(3)
150 #define SDIO_BUS_SPEED_UHSISEL_S	1
151 
152 /* for getting bus speed cap in card: 0x14h */
153 #define SDIO_BUS_SPEED_UHSICAP_M	BITFIELD_MASK(3)
154 #define SDIO_BUS_SPEED_UHSICAP_S	0
155 
156 /* for getting driver type CAP in card: 0x15h */
157 #define SDIO_BUS_DRVR_TYPE_CAP_M	BITFIELD_MASK(3)
158 #define SDIO_BUS_DRVR_TYPE_CAP_S	0
159 
160 /* for setting driver type selection in card: 0x15h */
161 #define SDIO_BUS_DRVR_TYPE_SEL_M	BITFIELD_MASK(2)
162 #define SDIO_BUS_DRVR_TYPE_SEL_S	4
163 
164 /* for getting async int support in card: 0x16h */
165 #define SDIO_BUS_ASYNCINT_CAP_M	BITFIELD_MASK(1)
166 #define SDIO_BUS_ASYNCINT_CAP_S	0
167 
168 /* for setting async int selection in card: 0x16h */
169 #define SDIO_BUS_ASYNCINT_SEL_M	BITFIELD_MASK(1)
170 #define SDIO_BUS_ASYNCINT_SEL_S	1
171 
172 /* brcm sepint */
173 #define SDIO_SEPINT_MASK	0x01	/* route sdpcmdev intr onto separate pad (chip-specific) */
174 #define SDIO_SEPINT_OE		0x02	/* 1 asserts output enable for above pad */
175 #define SDIO_SEPINT_ACT_HI	0x04	/* use active high interrupt level instead of active low */
176 
177 /* FBR structure for function 1-7, FBR addresses and register offsets */
178 typedef volatile struct {
179 	uint8	devctr;			/* device interface, CSA control */
180 	uint8	ext_dev;		/* extended standard I/O device type code */
181 	uint8	pwr_sel;		/* power selection support */
182 	uint8	PAD[6];			/* reserved */
183 
184 	uint8	cis_low;		/* CIS LSB */
185 	uint8	cis_mid;
186 	uint8	cis_high;		/* CIS MSB */
187 	uint8	csa_low;		/* code storage area, LSB */
188 	uint8	csa_mid;
189 	uint8	csa_high;		/* code storage area, MSB */
190 	uint8	csa_dat_win;		/* data access window to function */
191 
192 	uint8	fnx_blk_size[2];	/* block size, little endian */
193 } sdio_fbr_t;
194 
195 /* Maximum number of I/O funcs */
196 #define SDIOD_MAX_FUNCS			8
197 #define SDIOD_MAX_IOFUNCS		7
198 
199 /* SDIO Device FBR Start Address  */
200 #define SDIOD_FBR_STARTADDR		0x100
201 
202 /* SDIO Device FBR Size */
203 #define SDIOD_FBR_SIZE			0x100
204 
205 /* Macro to calculate FBR register base */
206 #define SDIOD_FBR_BASE(n)		((n) * 0x100)
207 
208 /* Function register offsets */
209 #define SDIOD_FBR_DEVCTR		0x00	/* basic info for function */
210 #define SDIOD_FBR_EXT_DEV		0x01	/* extended I/O device code */
211 #define SDIOD_FBR_PWR_SEL		0x02	/* power selection bits */
212 
213 /* SDIO Function CIS ptr offset */
214 #define SDIOD_FBR_CISPTR_0		0x09
215 #define SDIOD_FBR_CISPTR_1		0x0A
216 #define SDIOD_FBR_CISPTR_2		0x0B
217 
218 /* Code Storage Area pointer */
219 #define SDIOD_FBR_CSA_ADDR_0		0x0C
220 #define SDIOD_FBR_CSA_ADDR_1		0x0D
221 #define SDIOD_FBR_CSA_ADDR_2		0x0E
222 #define SDIOD_FBR_CSA_DATA		0x0F
223 
224 /* SDIO Function I/O Block Size */
225 #define SDIOD_FBR_BLKSIZE_0		0x10
226 #define SDIOD_FBR_BLKSIZE_1		0x11
227 
228 /* devctr */
229 #define SDIOD_FBR_DEVCTR_DIC	0x0f	/* device interface code */
230 #define SDIOD_FBR_DECVTR_CSA	0x40	/* CSA support flag */
231 #define SDIOD_FBR_DEVCTR_CSA_EN	0x80	/* CSA enabled */
232 /* interface codes */
233 #define SDIOD_DIC_NONE		0	/* SDIO standard interface is not supported */
234 #define SDIOD_DIC_UART		1
235 #define SDIOD_DIC_BLUETOOTH_A	2
236 #define SDIOD_DIC_BLUETOOTH_B	3
237 #define SDIOD_DIC_GPS		4
238 #define SDIOD_DIC_CAMERA	5
239 #define SDIOD_DIC_PHS		6
240 #define SDIOD_DIC_WLAN		7
241 #define SDIOD_DIC_EXT		0xf	/* extended device interface, read ext_dev register */
242 
243 /* pwr_sel */
244 #define SDIOD_PWR_SEL_SPS	0x01	/* supports power selection */
245 #define SDIOD_PWR_SEL_EPS	0x02	/* enable power selection (low-current mode) */
246 
247 /* misc defines */
248 #define SDIO_FUNC_0		0
249 #define SDIO_FUNC_1		1
250 #define SDIO_FUNC_2		2
251 #define SDIO_FUNC_3		3
252 #define SDIO_FUNC_4		4
253 #define SDIO_FUNC_5		5
254 #define SDIO_FUNC_6		6
255 #define SDIO_FUNC_7		7
256 
257 #define SD_CARD_TYPE_UNKNOWN	0	/* bad type or unrecognized */
258 #define SD_CARD_TYPE_IO		1	/* IO only card */
259 #define SD_CARD_TYPE_MEMORY	2	/* memory only card */
260 #define SD_CARD_TYPE_COMBO	3	/* IO and memory combo card */
261 
262 #define SDIO_MAX_BLOCK_SIZE	2048	/* maximum block size for block mode operation */
263 #define SDIO_MIN_BLOCK_SIZE	1	/* minimum block size for block mode operation */
264 
265 /* Card registers: status bit position */
266 #define CARDREG_STATUS_BIT_OUTOFRANGE		31
267 #define CARDREG_STATUS_BIT_COMCRCERROR		23
268 #define CARDREG_STATUS_BIT_ILLEGALCOMMAND	22
269 #define CARDREG_STATUS_BIT_ERROR		19
270 #define CARDREG_STATUS_BIT_IOCURRENTSTATE3	12
271 #define CARDREG_STATUS_BIT_IOCURRENTSTATE2	11
272 #define CARDREG_STATUS_BIT_IOCURRENTSTATE1	10
273 #define CARDREG_STATUS_BIT_IOCURRENTSTATE0	9
274 #define CARDREG_STATUS_BIT_FUN_NUM_ERROR	4
275 
276 
277 
278 #define SD_CMD_GO_IDLE_STATE		0	/* mandatory for SDIO */
279 #define SD_CMD_SEND_OPCOND		1
280 #define SD_CMD_MMC_SET_RCA		3
281 #define SD_CMD_IO_SEND_OP_COND		5	/* mandatory for SDIO */
282 #define SD_CMD_SELECT_DESELECT_CARD	7
283 #define SD_CMD_SEND_CSD			9
284 #define SD_CMD_SEND_CID			10
285 #define SD_CMD_STOP_TRANSMISSION	12
286 #define SD_CMD_SEND_STATUS		13
287 #define SD_CMD_GO_INACTIVE_STATE	15
288 #define SD_CMD_SET_BLOCKLEN		16
289 #define SD_CMD_READ_SINGLE_BLOCK	17
290 #define SD_CMD_READ_MULTIPLE_BLOCK	18
291 #define SD_CMD_WRITE_BLOCK		24
292 #define SD_CMD_WRITE_MULTIPLE_BLOCK	25
293 #define SD_CMD_PROGRAM_CSD		27
294 #define SD_CMD_SET_WRITE_PROT		28
295 #define SD_CMD_CLR_WRITE_PROT		29
296 #define SD_CMD_SEND_WRITE_PROT		30
297 #define SD_CMD_ERASE_WR_BLK_START	32
298 #define SD_CMD_ERASE_WR_BLK_END		33
299 #define SD_CMD_ERASE			38
300 #define SD_CMD_LOCK_UNLOCK		42
301 #define SD_CMD_IO_RW_DIRECT		52	/* mandatory for SDIO */
302 #define SD_CMD_IO_RW_EXTENDED		53	/* mandatory for SDIO */
303 #define SD_CMD_APP_CMD			55
304 #define SD_CMD_GEN_CMD			56
305 #define SD_CMD_READ_OCR			58
306 #define SD_CMD_CRC_ON_OFF		59	/* mandatory for SDIO */
307 #define SD_ACMD_SD_STATUS		13
308 #define SD_ACMD_SEND_NUM_WR_BLOCKS	22
309 #define SD_ACMD_SET_WR_BLOCK_ERASE_CNT	23
310 #define SD_ACMD_SD_SEND_OP_COND		41
311 #define SD_ACMD_SET_CLR_CARD_DETECT	42
312 #define SD_ACMD_SEND_SCR		51
313 
314 /* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */
315 #define SD_IO_OP_READ		0   /* Read_Write: Read */
316 #define SD_IO_OP_WRITE		1   /* Read_Write: Write */
317 #define SD_IO_RW_NORMAL		0   /* no RAW */
318 #define SD_IO_RW_RAW		1   /* RAW */
319 #define SD_IO_BYTE_MODE		0   /* Byte Mode */
320 #define SD_IO_BLOCK_MODE	1   /* BlockMode */
321 #define SD_IO_FIXED_ADDRESS	0   /* fix Address */
322 #define SD_IO_INCREMENT_ADDRESS	1   /* IncrementAddress */
323 
324 /* build SD_CMD_IO_RW_DIRECT Argument */
325 #define SDIO_IO_RW_DIRECT_ARG(rw, raw, func, addr, data) \
326 	((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((raw) & 1) << 27) | \
327 	 (((addr) & 0x1FFFF) << 9) | ((data) & 0xFF))
328 
329 /* build SD_CMD_IO_RW_EXTENDED Argument */
330 #define SDIO_IO_RW_EXTENDED_ARG(rw, blk, func, addr, inc_addr, count) \
331 	((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((blk) & 1) << 27) | \
332 	 (((inc_addr) & 1) << 26) | (((addr) & 0x1FFFF) << 9) | ((count) & 0x1FF))
333 
334 /* SDIO response parameters */
335 #define SD_RSP_NO_NONE			0
336 #define SD_RSP_NO_1			1
337 #define SD_RSP_NO_2			2
338 #define SD_RSP_NO_3			3
339 #define SD_RSP_NO_4			4
340 #define SD_RSP_NO_5			5
341 #define SD_RSP_NO_6			6
342 
343 	/* Modified R6 response (to CMD3) */
344 #define SD_RSP_MR6_COM_CRC_ERROR	0x8000
345 #define SD_RSP_MR6_ILLEGAL_COMMAND	0x4000
346 #define SD_RSP_MR6_ERROR		0x2000
347 
348 	/* Modified R1 in R4 Response (to CMD5) */
349 #define SD_RSP_MR1_SBIT			0x80
350 #define SD_RSP_MR1_PARAMETER_ERROR	0x40
351 #define SD_RSP_MR1_RFU5			0x20
352 #define SD_RSP_MR1_FUNC_NUM_ERROR	0x10
353 #define SD_RSP_MR1_COM_CRC_ERROR	0x08
354 #define SD_RSP_MR1_ILLEGAL_COMMAND	0x04
355 #define SD_RSP_MR1_RFU1			0x02
356 #define SD_RSP_MR1_IDLE_STATE		0x01
357 
358 	/* R5 response (to CMD52 and CMD53) */
359 #define SD_RSP_R5_COM_CRC_ERROR		0x80
360 #define SD_RSP_R5_ILLEGAL_COMMAND	0x40
361 #define SD_RSP_R5_IO_CURRENTSTATE1	0x20
362 #define SD_RSP_R5_IO_CURRENTSTATE0	0x10
363 #define SD_RSP_R5_ERROR			0x08
364 #define SD_RSP_R5_RFU			0x04
365 #define SD_RSP_R5_FUNC_NUM_ERROR	0x02
366 #define SD_RSP_R5_OUT_OF_RANGE		0x01
367 
368 #define SD_RSP_R5_ERRBITS		0xCB
369 
370 
371 /* ------------------------------------------------
372  *  SDIO Commands and responses
373  *
374  *  I/O only commands are:
375  *      CMD0, CMD3, CMD5, CMD7, CMD14, CMD15, CMD52, CMD53
376  * ------------------------------------------------
377  */
378 
379 /* SDIO Commands */
380 #define SDIOH_CMD_0		0
381 #define SDIOH_CMD_3		3
382 #define SDIOH_CMD_5		5
383 #define SDIOH_CMD_7		7
384 #define SDIOH_CMD_11		11
385 #define SDIOH_CMD_14		14
386 #define SDIOH_CMD_15		15
387 #define SDIOH_CMD_19		19
388 #define SDIOH_CMD_52		52
389 #define SDIOH_CMD_53		53
390 #define SDIOH_CMD_59		59
391 
392 /* SDIO Command Responses */
393 #define SDIOH_RSP_NONE		0
394 #define SDIOH_RSP_R1		1
395 #define SDIOH_RSP_R2		2
396 #define SDIOH_RSP_R3		3
397 #define SDIOH_RSP_R4		4
398 #define SDIOH_RSP_R5		5
399 #define SDIOH_RSP_R6		6
400 
401 /*
402  *  SDIO Response Error flags
403  */
404 #define SDIOH_RSP5_ERROR_FLAGS	0xCB
405 
406 /* ------------------------------------------------
407  * SDIO Command structures. I/O only commands are:
408  *
409  * 	CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53
410  * ------------------------------------------------
411  */
412 
413 #define CMD5_OCR_M		BITFIELD_MASK(24)
414 #define CMD5_OCR_S		0
415 
416 #define CMD5_S18R_M		BITFIELD_MASK(1)
417 #define CMD5_S18R_S		24
418 
419 #define CMD7_RCA_M		BITFIELD_MASK(16)
420 #define CMD7_RCA_S		16
421 
422 #define CMD14_RCA_M		BITFIELD_MASK(16)
423 #define CMD14_RCA_S		16
424 #define CMD14_SLEEP_M		BITFIELD_MASK(1)
425 #define CMD14_SLEEP_S		15
426 
427 #define CMD_15_RCA_M		BITFIELD_MASK(16)
428 #define CMD_15_RCA_S		16
429 
430 #define CMD52_DATA_M		BITFIELD_MASK(8)  /* Bits [7:0]    - Write Data/Stuff bits of CMD52
431 						   */
432 #define CMD52_DATA_S		0
433 #define CMD52_REG_ADDR_M	BITFIELD_MASK(17) /* Bits [25:9]   - register address */
434 #define CMD52_REG_ADDR_S	9
435 #define CMD52_RAW_M		BITFIELD_MASK(1)  /* Bit  27       - Read after Write flag */
436 #define CMD52_RAW_S		27
437 #define CMD52_FUNCTION_M	BITFIELD_MASK(3)  /* Bits [30:28]  - Function number */
438 #define CMD52_FUNCTION_S	28
439 #define CMD52_RW_FLAG_M		BITFIELD_MASK(1)  /* Bit  31       - R/W flag */
440 #define CMD52_RW_FLAG_S		31
441 
442 
443 #define CMD53_BYTE_BLK_CNT_M	BITFIELD_MASK(9) /* Bits [8:0]     - Byte/Block Count of CMD53 */
444 #define CMD53_BYTE_BLK_CNT_S	0
445 #define CMD53_REG_ADDR_M	BITFIELD_MASK(17) /* Bits [25:9]   - register address */
446 #define CMD53_REG_ADDR_S	9
447 #define CMD53_OP_CODE_M		BITFIELD_MASK(1)  /* Bit  26       - R/W Operation Code */
448 #define CMD53_OP_CODE_S		26
449 #define CMD53_BLK_MODE_M	BITFIELD_MASK(1)  /* Bit  27       - Block Mode */
450 #define CMD53_BLK_MODE_S	27
451 #define CMD53_FUNCTION_M	BITFIELD_MASK(3)  /* Bits [30:28]  - Function number */
452 #define CMD53_FUNCTION_S	28
453 #define CMD53_RW_FLAG_M		BITFIELD_MASK(1)  /* Bit  31       - R/W flag */
454 #define CMD53_RW_FLAG_S		31
455 
456 /* ------------------------------------------------------
457  * SDIO Command Response structures for SD1 and SD4 modes
458  *  -----------------------------------------------------
459  */
460 #define RSP4_IO_OCR_M		BITFIELD_MASK(24) /* Bits [23:0]  - Card's OCR Bits [23:0] */
461 #define RSP4_IO_OCR_S		0
462 
463 #define RSP4_S18A_M			BITFIELD_MASK(1) /* Bits [23:0]  - Card's OCR Bits [23:0] */
464 #define RSP4_S18A_S			24
465 
466 #define RSP4_STUFF_M		BITFIELD_MASK(3)  /* Bits [26:24] - Stuff bits */
467 #define RSP4_STUFF_S		24
468 #define RSP4_MEM_PRESENT_M	BITFIELD_MASK(1)  /* Bit  27      - Memory present */
469 #define RSP4_MEM_PRESENT_S	27
470 #define RSP4_NUM_FUNCS_M	BITFIELD_MASK(3)  /* Bits [30:28] - Number of I/O funcs */
471 #define RSP4_NUM_FUNCS_S	28
472 #define RSP4_CARD_READY_M	BITFIELD_MASK(1)  /* Bit  31      - SDIO card ready */
473 #define RSP4_CARD_READY_S	31
474 
475 #define RSP6_STATUS_M		BITFIELD_MASK(16) /* Bits [15:0]  - Card status bits [19,22,23,12:0]
476 						   */
477 #define RSP6_STATUS_S		0
478 #define RSP6_IO_RCA_M		BITFIELD_MASK(16) /* Bits [31:16] - RCA bits[31-16] */
479 #define RSP6_IO_RCA_S		16
480 
481 #define RSP1_AKE_SEQ_ERROR_M	BITFIELD_MASK(1)  /* Bit 3       - Authentication seq error */
482 #define RSP1_AKE_SEQ_ERROR_S	3
483 #define RSP1_APP_CMD_M		BITFIELD_MASK(1)  /* Bit 5       - Card expects ACMD */
484 #define RSP1_APP_CMD_S		5
485 #define RSP1_READY_FOR_DATA_M	BITFIELD_MASK(1)  /* Bit 8       - Ready for data (buff empty) */
486 #define RSP1_READY_FOR_DATA_S	8
487 #define RSP1_CURR_STATE_M	BITFIELD_MASK(4)  /* Bits [12:9] - State of card
488 						   * when Cmd was received
489 						   */
490 #define RSP1_CURR_STATE_S	9
491 #define RSP1_EARSE_RESET_M	BITFIELD_MASK(1)  /* Bit 13   - Erase seq cleared */
492 #define RSP1_EARSE_RESET_S	13
493 #define RSP1_CARD_ECC_DISABLE_M	BITFIELD_MASK(1)  /* Bit 14   - Card ECC disabled */
494 #define RSP1_CARD_ECC_DISABLE_S	14
495 #define RSP1_WP_ERASE_SKIP_M	BITFIELD_MASK(1)  /* Bit 15   - Partial blocks erased due to W/P */
496 #define RSP1_WP_ERASE_SKIP_S	15
497 #define RSP1_CID_CSD_OVERW_M	BITFIELD_MASK(1)  /* Bit 16   - Illegal write to CID or R/O bits
498 						   * of CSD
499 						   */
500 #define RSP1_CID_CSD_OVERW_S	16
501 #define RSP1_ERROR_M		BITFIELD_MASK(1)  /* Bit 19   - General/Unknown error */
502 #define RSP1_ERROR_S		19
503 #define RSP1_CC_ERROR_M		BITFIELD_MASK(1)  /* Bit 20   - Internal Card Control error */
504 #define RSP1_CC_ERROR_S		20
505 #define RSP1_CARD_ECC_FAILED_M	BITFIELD_MASK(1)  /* Bit 21   - Card internal ECC failed
506 						   * to correct data
507 						   */
508 #define RSP1_CARD_ECC_FAILED_S	21
509 #define RSP1_ILLEGAL_CMD_M	BITFIELD_MASK(1)  /* Bit 22   - Cmd not legal for the card state */
510 #define RSP1_ILLEGAL_CMD_S	22
511 #define RSP1_COM_CRC_ERROR_M	BITFIELD_MASK(1)  /* Bit 23   - CRC check of previous command failed
512 						   */
513 #define RSP1_COM_CRC_ERROR_S	23
514 #define RSP1_LOCK_UNLOCK_FAIL_M	BITFIELD_MASK(1)  /* Bit 24   - Card lock-unlock Cmd Seq error */
515 #define RSP1_LOCK_UNLOCK_FAIL_S	24
516 #define RSP1_CARD_LOCKED_M	BITFIELD_MASK(1)  /* Bit 25   - Card locked by the host */
517 #define RSP1_CARD_LOCKED_S	25
518 #define RSP1_WP_VIOLATION_M	BITFIELD_MASK(1)  /* Bit 26   - Attempt to program
519 						   * write-protected blocks
520 						   */
521 #define RSP1_WP_VIOLATION_S	26
522 #define RSP1_ERASE_PARAM_M	BITFIELD_MASK(1)  /* Bit 27   - Invalid erase blocks */
523 #define RSP1_ERASE_PARAM_S	27
524 #define RSP1_ERASE_SEQ_ERR_M	BITFIELD_MASK(1)  /* Bit 28   - Erase Cmd seq error */
525 #define RSP1_ERASE_SEQ_ERR_S	28
526 #define RSP1_BLK_LEN_ERR_M	BITFIELD_MASK(1)  /* Bit 29   - Block length error */
527 #define RSP1_BLK_LEN_ERR_S	29
528 #define RSP1_ADDR_ERR_M		BITFIELD_MASK(1)  /* Bit 30   - Misaligned address */
529 #define RSP1_ADDR_ERR_S		30
530 #define RSP1_OUT_OF_RANGE_M	BITFIELD_MASK(1)  /* Bit 31   - Cmd arg was out of range */
531 #define RSP1_OUT_OF_RANGE_S	31
532 
533 
534 #define RSP5_DATA_M		BITFIELD_MASK(8)  /* Bits [0:7]   - data */
535 #define RSP5_DATA_S		0
536 #define RSP5_FLAGS_M		BITFIELD_MASK(8)  /* Bit  [15:8]  - Rsp flags */
537 #define RSP5_FLAGS_S		8
538 #define RSP5_STUFF_M		BITFIELD_MASK(16) /* Bits [31:16] - Stuff bits */
539 #define RSP5_STUFF_S		16
540 
541 /* ----------------------------------------------
542  * SDIO Command Response structures for SPI mode
543  * ----------------------------------------------
544  */
545 #define SPIRSP4_IO_OCR_M	BITFIELD_MASK(16) /* Bits [15:0]    - Card's OCR Bits [23:8] */
546 #define SPIRSP4_IO_OCR_S	0
547 #define SPIRSP4_STUFF_M		BITFIELD_MASK(3)  /* Bits [18:16]   - Stuff bits */
548 #define SPIRSP4_STUFF_S		16
549 #define SPIRSP4_MEM_PRESENT_M	BITFIELD_MASK(1)  /* Bit  19        - Memory present */
550 #define SPIRSP4_MEM_PRESENT_S	19
551 #define SPIRSP4_NUM_FUNCS_M	BITFIELD_MASK(3)  /* Bits [22:20]   - Number of I/O funcs */
552 #define SPIRSP4_NUM_FUNCS_S	20
553 #define SPIRSP4_CARD_READY_M	BITFIELD_MASK(1)  /* Bit  23        - SDIO card ready */
554 #define SPIRSP4_CARD_READY_S	23
555 #define SPIRSP4_IDLE_STATE_M	BITFIELD_MASK(1)  /* Bit  24        - idle state */
556 #define SPIRSP4_IDLE_STATE_S	24
557 #define SPIRSP4_ILLEGAL_CMD_M	BITFIELD_MASK(1)  /* Bit  26        - Illegal Cmd error */
558 #define SPIRSP4_ILLEGAL_CMD_S	26
559 #define SPIRSP4_COM_CRC_ERROR_M	BITFIELD_MASK(1)  /* Bit  27        - COM CRC error */
560 #define SPIRSP4_COM_CRC_ERROR_S	27
561 #define SPIRSP4_FUNC_NUM_ERROR_M	BITFIELD_MASK(1)  /* Bit  28        - Function number error
562 							   */
563 #define SPIRSP4_FUNC_NUM_ERROR_S	28
564 #define SPIRSP4_PARAM_ERROR_M	BITFIELD_MASK(1)  /* Bit  30        - Parameter Error Bit */
565 #define SPIRSP4_PARAM_ERROR_S	30
566 #define SPIRSP4_START_BIT_M	BITFIELD_MASK(1)  /* Bit  31        - Start Bit */
567 #define SPIRSP4_START_BIT_S	31
568 
569 #define SPIRSP5_DATA_M			BITFIELD_MASK(8)  /* Bits [23:16]   - R/W Data */
570 #define SPIRSP5_DATA_S			16
571 #define SPIRSP5_IDLE_STATE_M		BITFIELD_MASK(1)  /* Bit  24        - Idle state */
572 #define SPIRSP5_IDLE_STATE_S		24
573 #define SPIRSP5_ILLEGAL_CMD_M		BITFIELD_MASK(1)  /* Bit  26        - Illegal Cmd error */
574 #define SPIRSP5_ILLEGAL_CMD_S		26
575 #define SPIRSP5_COM_CRC_ERROR_M		BITFIELD_MASK(1)  /* Bit  27        - COM CRC error */
576 #define SPIRSP5_COM_CRC_ERROR_S		27
577 #define SPIRSP5_FUNC_NUM_ERROR_M	BITFIELD_MASK(1)  /* Bit  28        - Function number error
578 							   */
579 #define SPIRSP5_FUNC_NUM_ERROR_S	28
580 #define SPIRSP5_PARAM_ERROR_M		BITFIELD_MASK(1)  /* Bit  30        - Parameter Error Bit */
581 #define SPIRSP5_PARAM_ERROR_S		30
582 #define SPIRSP5_START_BIT_M		BITFIELD_MASK(1)  /* Bit  31        - Start Bit */
583 #define SPIRSP5_START_BIT_S		31
584 
585 /* RSP6 card status format; Pg 68 Physical Layer spec v 1.10 */
586 #define RSP6STAT_AKE_SEQ_ERROR_M	BITFIELD_MASK(1)  /* Bit 3	- Authentication seq error
587 							   */
588 #define RSP6STAT_AKE_SEQ_ERROR_S	3
589 #define RSP6STAT_APP_CMD_M		BITFIELD_MASK(1)  /* Bit 5	- Card expects ACMD */
590 #define RSP6STAT_APP_CMD_S		5
591 #define RSP6STAT_READY_FOR_DATA_M	BITFIELD_MASK(1)  /* Bit 8	- Ready for data
592 							   * (buff empty)
593 							   */
594 #define RSP6STAT_READY_FOR_DATA_S	8
595 #define RSP6STAT_CURR_STATE_M		BITFIELD_MASK(4)  /* Bits [12:9] - Card state at
596 							   * Cmd reception
597 							   */
598 #define RSP6STAT_CURR_STATE_S		9
599 #define RSP6STAT_ERROR_M		BITFIELD_MASK(1)  /* Bit 13  - General/Unknown error Bit 19
600 							   */
601 #define RSP6STAT_ERROR_S		13
602 #define RSP6STAT_ILLEGAL_CMD_M		BITFIELD_MASK(1)  /* Bit 14  - Illegal cmd for
603 							   * card state Bit 22
604 							   */
605 #define RSP6STAT_ILLEGAL_CMD_S		14
606 #define RSP6STAT_COM_CRC_ERROR_M	BITFIELD_MASK(1)  /* Bit 15  - CRC previous command
607 							   * failed Bit 23
608 							   */
609 #define RSP6STAT_COM_CRC_ERROR_S	15
610 
611 #define SDIOH_XFER_TYPE_READ    SD_IO_OP_READ
612 #define SDIOH_XFER_TYPE_WRITE   SD_IO_OP_WRITE
613 
614 /* command issue options */
615 #define CMD_OPTION_DEFAULT	0
616 #define CMD_OPTION_TUNING	1
617 #endif /* _SDIO_H */
618