1 #ifndef _INC_MUSYCC_H_ 2 #define _INC_MUSYCC_H_ 3 4 /*----------------------------------------------------------------------------- 5 * musycc.h - Multichannel Synchronous Communications Controller 6 * CN8778/8474A/8472A/8471A 7 * 8 * Copyright (C) 2002-2005 SBE, Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * For further information, contact via email: support@sbei.com 21 * SBE, Inc. San Ramon, California U.S.A. 22 *----------------------------------------------------------------------------- 23 */ 24 25 #include <linux/types.h> 26 27 #define VINT8 volatile u_int8_t 28 #define VINT32 volatile u_int32_t 29 30 #include "pmcc4_defs.h" 31 32 33 /*------------------------------------------------------------------------ 34 // Vendor, Board Identification definitions 35 //------------------------------------------------------------------------ 36 */ 37 38 #define PCI_VENDOR_ID_CONEXANT 0x14f1 39 #define PCI_DEVICE_ID_CN8471 0x8471 40 #define PCI_DEVICE_ID_CN8472 0x8472 41 #define PCI_DEVICE_ID_CN8474 0x8474 42 #define PCI_DEVICE_ID_CN8478 0x8478 43 #define PCI_DEVICE_ID_CN8500 0x8500 44 #define PCI_DEVICE_ID_CN8501 0x8501 45 #define PCI_DEVICE_ID_CN8502 0x8502 46 #define PCI_DEVICE_ID_CN8503 0x8503 47 48 #define INT_QUEUE_SIZE MUSYCC_NIQD 49 50 /* RAM image of MUSYCC registers laid out as a C structure */ 51 struct musycc_groupr 52 { 53 VINT32 thp[32]; /* Transmit Head Pointer [5-29] */ 54 VINT32 tmp[32]; /* Transmit Message Pointer [5-30] */ 55 VINT32 rhp[32]; /* Receive Head Pointer [5-29] */ 56 VINT32 rmp[32]; /* Receive Message Pointer [5-30] */ 57 VINT8 ttsm[128]; /* Time Slot Map [5-22] */ 58 VINT8 tscm[256]; /* Subchannel Map [5-24] */ 59 VINT32 tcct[32]; /* Channel Configuration [5-26] */ 60 VINT8 rtsm[128]; /* Time Slot Map [5-22] */ 61 VINT8 rscm[256]; /* Subchannel Map [5-24] */ 62 VINT32 rcct[32]; /* Channel Configuration [5-26] */ 63 VINT32 __glcd; /* Global Configuration Descriptor [5-10] */ 64 VINT32 __iqp; /* Interrupt Queue Pointer [5-36] */ 65 VINT32 __iql; /* Interrupt Queue Length [5-36] */ 66 VINT32 grcd; /* Group Configuration Descriptor [5-16] */ 67 VINT32 mpd; /* Memory Protection Descriptor [5-18] */ 68 VINT32 mld; /* Message Length Descriptor [5-20] */ 69 VINT32 pcd; /* Port Configuration Descriptor [5-19] */ 70 }; 71 72 /* hardware MUSYCC registers laid out as a C structure */ 73 struct musycc_globalr 74 { 75 VINT32 gbp; /* Group Base Pointer */ 76 VINT32 dacbp; /* Dual Address Cycle Base Pointer */ 77 VINT32 srd; /* Service Request Descriptor */ 78 VINT32 isd; /* Interrupt Service Descriptor */ 79 /* 80 * adjust __thp due to above 4 registers, which are not contained 81 * within musycc_groupr[]. All __XXX[] are just place holders, 82 * anyhow. 83 */ 84 VINT32 __thp[32 - 4]; /* Transmit Head Pointer [5-29] */ 85 VINT32 __tmp[32]; /* Transmit Message Pointer [5-30] */ 86 VINT32 __rhp[32]; /* Receive Head Pointer [5-29] */ 87 VINT32 __rmp[32]; /* Receive Message Pointer [5-30] */ 88 VINT8 ttsm[128]; /* Time Slot Map [5-22] */ 89 VINT8 tscm[256]; /* Subchannel Map [5-24] */ 90 VINT32 tcct[32]; /* Channel Configuration [5-26] */ 91 VINT8 rtsm[128]; /* Time Slot Map [5-22] */ 92 VINT8 rscm[256]; /* Subchannel Map [5-24] */ 93 VINT32 rcct[32]; /* Channel Configuration [5-26] */ 94 VINT32 glcd; /* Global Configuration Descriptor [5-10] */ 95 VINT32 iqp; /* Interrupt Queue Pointer [5-36] */ 96 VINT32 iql; /* Interrupt Queue Length [5-36] */ 97 VINT32 grcd; /* Group Configuration Descriptor [5-16] */ 98 VINT32 mpd; /* Memory Protection Descriptor [5-18] */ 99 VINT32 mld; /* Message Length Descriptor [5-20] */ 100 VINT32 pcd; /* Port Configuration Descriptor [5-19] */ 101 VINT32 rbist; /* Receive BIST status [5-4] */ 102 VINT32 tbist; /* Receive BIST status [5-4] */ 103 }; 104 105 /* Global Config Descriptor bit macros */ 106 #define MUSYCC_GCD_ECLK_ENABLE 0x00000800 /* EBUS clock enable */ 107 #define MUSYCC_GCD_INTEL_SELECT 0x00000400 /* MPU type select */ 108 #define MUSYCC_GCD_INTA_DISABLE 0x00000008 /* PCI INTA disable */ 109 #define MUSYCC_GCD_INTB_DISABLE 0x00000004 /* PCI INTB disable */ 110 #define MUSYCC_GCD_BLAPSE 12 /* Position index for BLAPSE bit 111 * field */ 112 #define MUSYCC_GCD_ALAPSE 8 /* Position index for ALAPSE bit 113 * field */ 114 #define MUSYCC_GCD_ELAPSE 4 /* Position index for ELAPSE bit 115 * field */ 116 #define MUSYCC_GCD_PORTMAP_3 3 /* Reserved */ 117 #define MUSYCC_GCD_PORTMAP_2 2 /* Port 0=>Grp 0,1,2,3; Port 1=>Grp 118 * 4,5,6,7 */ 119 #define MUSYCC_GCD_PORTMAP_1 1 /* Port 0=>Grp 0,1; Port 1=>Grp 2,3, 120 * etc... */ 121 #define MUSYCC_GCD_PORTMAP_0 0 /* Port 0=>Grp 0; Port 1=>Grp 2, 122 * etc... */ 123 124 /* and board specific assignments... */ 125 #ifdef SBE_WAN256T3_ENABLE 126 #define BLAPSE_VAL 0 127 #define ALAPSE_VAL 0 128 #define ELAPSE_VAL 7 129 #define PORTMAP_VAL MUSYCC_GCD_PORTMAP_2 130 #endif 131 132 #ifdef SBE_PMCC4_ENABLE 133 #define BLAPSE_VAL 7 134 #define ALAPSE_VAL 3 135 #define ELAPSE_VAL 7 136 #define PORTMAP_VAL MUSYCC_GCD_PORTMAP_0 137 #endif 138 139 #define GCD_MAGIC (((BLAPSE_VAL)<<(MUSYCC_GCD_BLAPSE)) | \ 140 ((ALAPSE_VAL)<<(MUSYCC_GCD_ALAPSE)) | \ 141 ((ELAPSE_VAL)<<(MUSYCC_GCD_ELAPSE)) | \ 142 (MUSYCC_GCD_ECLK_ENABLE) | PORTMAP_VAL) 143 144 /* Group Config Descriptor bit macros */ 145 #define MUSYCC_GRCD_RX_ENABLE 0x00000001 /* Enable receive processing */ 146 #define MUSYCC_GRCD_TX_ENABLE 0x00000002 /* Enable transmit processing */ 147 #define MUSYCC_GRCD_SUBCHAN_DISABLE 0x00000004 /* Master disable for 148 * subchanneling */ 149 #define MUSYCC_GRCD_OOFMP_DISABLE 0x00000008 /* Out of Frame message 150 * processing disabled all 151 * channels */ 152 #define MUSYCC_GRCD_OOFIRQ_DISABLE 0x00000010 /* Out of Frame/In Frame irqs 153 * disabled */ 154 #define MUSYCC_GRCD_COFAIRQ_DISABLE 0x00000020 /* Change of Frame Alignment 155 * irq disabled */ 156 #define MUSYCC_GRCD_INHRBSD 0x00000100 /* Receive Buffer Status 157 * overwrite disabled */ 158 #define MUSYCC_GRCD_INHTBSD 0x00000200 /* Transmit Buffer Status 159 * overwrite disabled */ 160 #define MUSYCC_GRCD_SF_ALIGN 0x00008000 /* External frame sync */ 161 #define MUSYCC_GRCD_MC_ENABLE 0x00000040 /* Message configuration bits 162 * copy enable. Conexant sez 163 * turn this on */ 164 #define MUSYCC_GRCD_POLLTH_16 0x00000001 /* Poll every 16th frame */ 165 #define MUSYCC_GRCD_POLLTH_32 0x00000002 /* Poll every 32nd frame */ 166 #define MUSYCC_GRCD_POLLTH_64 0x00000003 /* Poll every 64th frame */ 167 #define MUSYCC_GRCD_POLLTH_SHIFT 10 /* Position index for poll throttle 168 * bit field */ 169 #define MUSYCC_GRCD_SUERM_THRESH_SHIFT 16 /* Position index for SUERM 170 * count threshold */ 171 172 /* Port Config Descriptor bit macros */ 173 #define MUSYCC_PCD_E1X2_MODE 2 /* Port mode in bits 0-2. T1 and E1 */ 174 #define MUSYCC_PCD_E1X4_MODE 3 /* are defined in cn847x.h */ 175 #define MUSYCC_PCD_NX64_MODE 4 176 #define MUSYCC_PCD_TXDATA_RISING 0x00000010 /* Sample Tx data on TCLK 177 * rising edge */ 178 #define MUSYCC_PCD_TXSYNC_RISING 0x00000020 /* Sample Tx frame sync on 179 * TCLK rising edge */ 180 #define MUSYCC_PCD_RXDATA_RISING 0x00000040 /* Sample Rx data on RCLK 181 * rising edge */ 182 #define MUSYCC_PCD_RXSYNC_RISING 0x00000080 /* Sample Rx frame sync on 183 * RCLK rising edge */ 184 #define MUSYCC_PCD_ROOF_RISING 0x00000100 /* Sample Rx Out Of Frame 185 * signal on RCLK rising edge */ 186 #define MUSYCC_PCD_TX_DRIVEN 0x00000200 /* No mapped timeslots causes 187 * logic 1 on output, else 188 * tristate */ 189 #define MUSYCC_PCD_PORTMODE_MASK 0xfffffff8 /* For changing the port mode 190 * between E1 and T1 */ 191 192 /* Time Slot Descriptor bit macros */ 193 #define MUSYCC_TSD_MODE_64KBPS 4 194 #define MUSYCC_TSD_MODE_56KBPS 5 195 #define MUSYCC_TSD_SUBCHANNEL_WO_FIRST 6 196 #define MUSYCC_TSD_SUBCHANNEL_WITH_FIRST 7 197 198 /* Message Descriptor bit macros */ 199 #define MUSYCC_MDT_BASE03_ADDR 0x00006000 200 201 /* Channel Config Descriptor bit macros */ 202 #define MUSYCC_CCD_BUFIRQ_DISABLE 0x00000002 /* BUFF and ONR irqs disabled */ 203 #define MUSYCC_CCD_EOMIRQ_DISABLE 0x00000004 /* EOM irq disabled */ 204 #define MUSYCC_CCD_MSGIRQ_DISABLE 0x00000008 /* LNG, FCS, ALIGN, and ABT 205 * irqs disabled */ 206 #define MUSYCC_CCD_IDLEIRQ_DISABLE 0x00000010 /* CHABT, CHIC, and SHT irqs 207 * disabled */ 208 #define MUSYCC_CCD_FILTIRQ_DISABLE 0x00000020 /* SFILT irq disabled */ 209 #define MUSYCC_CCD_SDECIRQ_DISABLE 0x00000040 /* SDEC irq disabled */ 210 #define MUSYCC_CCD_SINCIRQ_DISABLE 0x00000080 /* SINC irq disabled */ 211 #define MUSYCC_CCD_SUERIRQ_DISABLE 0x00000100 /* SUERR irq disabled */ 212 #define MUSYCC_CCD_FCS_XFER 0x00000200 /* Propagate FCS along with 213 * received data */ 214 #define MUSYCC_CCD_PROTO_SHIFT 12 /* Position index for protocol bit 215 * field */ 216 #define MUSYCC_CCD_TRANS 0 /* Protocol mode in bits 12-14 */ 217 #define MUSYCC_CCD_SS7 1 218 #define MUSYCC_CCD_HDLC_FCS16 2 219 #define MUSYCC_CCD_HDLC_FCS32 3 220 #define MUSYCC_CCD_EOPIRQ_DISABLE 0x00008000 /* EOP irq disabled */ 221 #define MUSYCC_CCD_INVERT_DATA 0x00800000 /* Invert data */ 222 #define MUSYCC_CCD_MAX_LENGTH 10 /* Position index for max length bit 223 * field */ 224 #define MUSYCC_CCD_BUFFER_LENGTH 16 /* Position index for internal data 225 * buffer length */ 226 #define MUSYCC_CCD_BUFFER_LOC 24 /* Position index for internal data 227 * buffer starting location */ 228 229 /**************************************************************************** 230 * Interrupt Descriptor Information */ 231 232 #define INT_EMPTY_ENTRY 0xfeedface 233 #define INT_EMPTY_ENTRY2 0xdeadface 234 235 /**************************************************************************** 236 * Interrupt Status Descriptor 237 * 238 * NOTE: One must first fetch the value of the interrupt status descriptor 239 * into a local variable, then pass that value into the read macros. This 240 * is required to avoid race conditions. 241 ***/ 242 243 #define INTRPTS_NEXTINT_M 0x7FFF0000 244 #define INTRPTS_NEXTINT_S 16 245 #define INTRPTS_NEXTINT(x) ((x & INTRPTS_NEXTINT_M) >> INTRPTS_NEXTINT_S) 246 247 #define INTRPTS_INTFULL_M 0x00008000 248 #define INTRPTS_INTFULL_S 15 249 #define INTRPTS_INTFULL(x) ((x & INTRPTS_INTFULL_M) >> INTRPTS_INTFULL_S) 250 251 #define INTRPTS_INTCNT_M 0x00007FFF 252 #define INTRPTS_INTCNT_S 0 253 #define INTRPTS_INTCNT(x) ((x & INTRPTS_INTCNT_M) >> INTRPTS_INTCNT_S) 254 255 256 /**************************************************************************** 257 * Interrupt Descriptor 258 ***/ 259 260 #define INTRPT_DIR_M 0x80000000 261 #define INTRPT_DIR_S 31 262 #define INTRPT_DIR(x) ((x & INTRPT_DIR_M) >> INTRPT_DIR_S) 263 264 #define INTRPT_GRP_M 0x60000000 265 #define INTRPT_GRP_MSB_M 0x00004000 266 #define INTRPT_GRP_S 29 267 #define INTRPT_GRP_MSB_S 12 268 #define INTRPT_GRP(x) (((x & INTRPT_GRP_M) >> INTRPT_GRP_S) | \ 269 ((x & INTRPT_GRP_MSB_M) >> INTRPT_GRP_MSB_S)) 270 271 #define INTRPT_CH_M 0x1F000000 272 #define INTRPT_CH_S 24 273 #define INTRPT_CH(x) ((x & INTRPT_CH_M) >> INTRPT_CH_S) 274 275 #define INTRPT_EVENT_M 0x00F00000 276 #define INTRPT_EVENT_S 20 277 #define INTRPT_EVENT(x) ((x & INTRPT_EVENT_M) >> INTRPT_EVENT_S) 278 279 #define INTRPT_ERROR_M 0x000F0000 280 #define INTRPT_ERROR_S 16 281 #define INTRPT_ERROR(x) ((x & INTRPT_ERROR_M) >> INTRPT_ERROR_S) 282 283 #define INTRPT_ILOST_M 0x00008000 284 #define INTRPT_ILOST_S 15 285 #define INTRPT_ILOST(x) ((x & INTRPT_ILOST_M) >> INTRPT_ILOST_S) 286 287 #define INTRPT_PERR_M 0x00004000 288 #define INTRPT_PERR_S 14 289 #define INTRPT_PERR(x) ((x & INTRPT_PERR_M) >> INTRPT_PERR_S) 290 291 #define INTRPT_BLEN_M 0x00003FFF 292 #define INTRPT_BLEN_S 0 293 #define INTRPT_BLEN(x) ((x & INTRPT_BLEN_M) >> INTRPT_BLEN_S) 294 295 296 /* Buffer Descriptor bit macros */ 297 #define OWNER_BIT 0x80000000 /* Set for MUSYCC owner on xmit, host 298 * owner on receive */ 299 #define HOST_TX_OWNED 0x00000000 /* Host owns descriptor */ 300 #define MUSYCC_TX_OWNED 0x80000000 /* MUSYCC owns descriptor */ 301 #define HOST_RX_OWNED 0x80000000 /* Host owns descriptor */ 302 #define MUSYCC_RX_OWNED 0x00000000 /* MUSYCC owns descriptor */ 303 304 #define POLL_DISABLED 0x40000000 /* MUSYCC not allowed to poll buffer 305 * for ownership */ 306 #define EOMIRQ_ENABLE 0x20000000 /* This buffer contains the end of 307 * the message */ 308 #define EOBIRQ_ENABLE 0x10000000 /* EOB irq enabled */ 309 #define PADFILL_ENABLE 0x01000000 /* Enable padfill */ 310 #define REPEAT_BIT 0x00008000 /* Bit on for FISU descriptor */ 311 #define LENGTH_MASK 0X3fff /* This part of status descriptor is 312 * length */ 313 #define IDLE_CODE 25 /* Position index for idle code (2 314 * bits) */ 315 #define EXTRA_FLAGS 16 /* Position index for minimum flags 316 * between messages (8 bits) */ 317 #define IDLE_CODE_MASK 0x03 /* Gets rid of garbage before the 318 * pattern is OR'd in */ 319 #define EXTRA_FLAGS_MASK 0xff /* Gets rid of garbage before the 320 * pattern is OR'd in */ 321 #define PCI_PERMUTED_OWNER_BIT 0x00000080 /* For flipping the bit on 322 * the polled mode descriptor */ 323 324 /* Service Request Descriptor bit macros */ 325 #define SREQ 8 /* Position index for service request bit 326 * field */ 327 #define SR_NOOP (0<<(SREQ)) /* No Operation. Generates SACK */ 328 #define SR_CHIP_RESET (1<<(SREQ)) /* Soft chip reset */ 329 #define SR_GROUP_RESET (2<<(SREQ)) /* Group reset */ 330 #define SR_GLOBAL_INIT (4<<(SREQ)) /* Global init: read global 331 * config deswc and interrupt 332 * queue desc */ 333 #define SR_GROUP_INIT (5<<(SREQ)) /* Group init: read Timeslot 334 * and Subchannel maps, 335 * Channel Config, */ 336 /* 337 * Group Config, Memory Protect, Message Length, and Port Config 338 * Descriptors 339 */ 340 #define SR_CHANNEL_ACTIVATE (8<<(SREQ)) /* Init channel, read Head 341 * Pointer, process first 342 * Message Descriptor */ 343 #define SR_GCHANNEL_MASK 0x001F /* channel portion (gchan) */ 344 #define SR_CHANNEL_DEACTIVATE (9<<(SREQ)) /* Stop channel processing */ 345 #define SR_JUMP (10<<(SREQ)) /* a: Process new Message 346 * List */ 347 #define SR_CHANNEL_CONFIG (11<<(SREQ)) /* b: Read channel 348 * Configuration Descriptor */ 349 #define SR_GLOBAL_CONFIG (16<<(SREQ)) /* 10: Read Global 350 * Configuration Descriptor */ 351 #define SR_INTERRUPT_Q (17<<(SREQ)) /* 11: Read Interrupt Queue 352 * Descriptor */ 353 #define SR_GROUP_CONFIG (18<<(SREQ)) /* 12: Read Group 354 * Configuration Descriptor */ 355 #define SR_MEMORY_PROTECT (19<<(SREQ)) /* 13: Read Memory Protection 356 * Descriptor */ 357 #define SR_MESSAGE_LENGTH (20<<(SREQ)) /* 14: Read Message Length 358 * Descriptor */ 359 #define SR_PORT_CONFIG (21<<(SREQ)) /* 15: Read Port 360 * Configuration Descriptor */ 361 #define SR_TIMESLOT_MAP (24<<(SREQ)) /* 18: Read Timeslot Map */ 362 #define SR_SUBCHANNEL_MAP (25<<(SREQ)) /* 19: Read Subchannel Map */ 363 #define SR_CHAN_CONFIG_TABLE (26<<(SREQ)) /* 20: Read Channel 364 * Configuration Table for 365 * the group */ 366 #define SR_TX_DIRECTION 0x00000020 /* Transmit direction bit. 367 * Bit off indicates receive 368 * direction */ 369 #define SR_RX_DIRECTION 0x00000000 370 371 /* Interrupt Descriptor bit macros */ 372 #define GROUP10 29 /* Position index for the 2 LS group 373 * bits */ 374 #define CHANNEL 24 /* Position index for channel bits */ 375 #define INT_IQD_TX 0x80000000 376 #define INT_IQD_GRP 0x60000000 377 #define INT_IQD_CHAN 0x1f000000 378 #define INT_IQD_EVENT 0x00f00000 379 #define INT_IQD_ERROR 0x000f0000 380 #define INT_IQD_ILOST 0x00008000 381 #define INT_IQD_PERR 0x00004000 382 #define INT_IQD_BLEN 0x00003fff 383 384 /* Interrupt Descriptor Events */ 385 #define EVE_EVENT 20 /* Position index for event bits */ 386 #define EVE_NONE 0 /* No event to report in this 387 * interrupt */ 388 #define EVE_SACK 1 /* Service Request acknowledge */ 389 #define EVE_EOB 2 /* End of Buffer */ 390 #define EVE_EOM 3 /* End of Message */ 391 #define EVE_EOP 4 /* End of Padfill */ 392 #define EVE_CHABT 5 /* Change to Abort Code */ 393 #define EVE_CHIC 6 /* Change to Idle Code */ 394 #define EVE_FREC 7 /* Frame Recovery */ 395 #define EVE_SINC 8 /* MTP2 SUERM Increment */ 396 #define EVE_SDEC 9 /* MTP2 SUERM Decrement */ 397 #define EVE_SFILT 10 /* MTP2 SUERM Filtered Message */ 398 /* Interrupt Descriptor Errors */ 399 #define ERR_ERRORS 16 /* Position index for error bits */ 400 #define ERR_BUF 1 /* Buffer Error */ 401 #define ERR_COFA 2 /* Change of Frame Alignment Error */ 402 #define ERR_ONR 3 /* Owner Bit Error */ 403 #define ERR_PROT 4 /* Memory Protection Error */ 404 #define ERR_OOF 8 /* Out of Frame Error */ 405 #define ERR_FCS 9 /* FCS Error */ 406 #define ERR_ALIGN 10 /* Octet Alignment Error */ 407 #define ERR_ABT 11 /* Abort Termination */ 408 #define ERR_LNG 12 /* Long Message Error */ 409 #define ERR_SHT 13 /* Short Message Error */ 410 #define ERR_SUERR 14 /* SUERM threshold exceeded */ 411 #define ERR_PERR 15 /* PCI Parity Error */ 412 /* Other Stuff */ 413 #define TRANSMIT_DIRECTION 0x80000000 /* Transmit direction bit. Bit off 414 * indicates receive direction */ 415 #define ILOST 0x00008000 /* Interrupt Lost */ 416 #define GROUPMSB 0x00004000 /* Group number MSB */ 417 #define SACK_IMAGE 0x00100000 /* Used in IRQ for semaphore test */ 418 #define INITIAL_STATUS 0x10000 /* IRQ status should be this after 419 * reset */ 420 421 /* This must be defined on an entire channel group (Port) basis */ 422 #define SUERM_THRESHOLD 0x1f 423 424 #undef VINT32 425 #undef VINT8 426 427 #endif /*** _INC_MUSYCC_H_ ***/ 428 429 /*** End-of-File ***/ 430