Searched refs:EXYNOS_DP_SYS_CTL_1 (Results 1 – 2 of 2) sorted by relevance
111 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_reset()970 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_init_video()1012 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_is_slave_video_stream_clock_on()1013 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_is_slave_video_stream_clock_on()1015 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_is_slave_video_stream_clock_on()
41 #define EXYNOS_DP_SYS_CTL_1 0x600 macro