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Searched refs:FPA0 (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/gma500/
Dcdv_intel_display.c981 crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0); in cdv_intel_crtc_save()
1047 REG_READ(pipeA ? FPA0 : FPB0), in cdv_intel_crtc_restore()
1092 REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0); in cdv_intel_crtc_restore()
1093 REG_READ(pipeA ? FPA0 : FPB0); in cdv_intel_crtc_restore()
1310 fp = REG_READ((pipe == 0) ? FPA0 : FPB0); in cdv_intel_crtc_clock_get()
Dpsb_intel_display.c595 int fp_reg = (pipe == 0) ? FPA0 : FPB0; in psb_intel_crtc_mode_set()
873 crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0); in psb_intel_crtc_save()
922 REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0); in psb_intel_crtc_restore()
923 REG_READ(pipeA ? FPA0 : FPB0); in psb_intel_crtc_restore()
1128 fp = REG_READ((pipe == 0) ? FPA0 : FPB0); in psb_intel_crtc_clock_get()
Dpsb_intel_reg.h334 #define FPA0 0x06040 macro
/drivers/video/intelfb/
Dintelfbhw.h166 #define FPA0 0x06040 macro
Dintelfbhw.c534 hw->fpa0 = INREG(FPA0); in intelfbhw_read_hw_state()
1343 fp0_reg = FPA0; in intelfbhw_program_mode()