Searched refs:FPGA_XD_PULL_CTL_EN1 (Results 1 – 4 of 4) sorted by relevance
97 #define FPGA_XD_PULL_CTL_EN1 0xFE macro
385 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3)); in reset_xd()426 (FPGA_XD_PULL_CTL_EN1 & in reset_xd()457 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2)); in reset_xd()
549 #define FPGA_XD_PULL_CTL_EN1 0xFE macro
463 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) | 0x20); in reset_xd()491 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) | 0x20); in reset_xd()518 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) | 0x20); in reset_xd()