1 /*
2 * arch/arm/mach-lpc32xx/gpiolib.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/io.h>
22 #include <linux/errno.h>
23 #include <linux/gpio.h>
24
25 #include <mach/hardware.h>
26 #include <mach/platform.h>
27 #include <mach/gpio-lpc32xx.h>
28
29 #define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
30 #define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
31 #define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
32 #define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
33 #define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
34 #define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
35 #define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
36 #define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
37 #define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
38 #define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
39 #define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
40 #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
41 #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
42 #define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
43 #define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
44 #define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
45 #define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
46 #define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
47 #define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
48 #define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
49 #define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
50 #define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
51 #define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
52 #define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
53 #define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
54 #define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
55 #define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
56
57 #define GPIO012_PIN_TO_BIT(x) (1 << (x))
58 #define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
59 #define GPO3_PIN_TO_BIT(x) (1 << (x))
60 #define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
61 #define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
62 #define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
63 #define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
64 #define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
65 #define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
66
67 struct gpio_regs {
68 void __iomem *inp_state;
69 void __iomem *outp_state;
70 void __iomem *outp_set;
71 void __iomem *outp_clr;
72 void __iomem *dir_set;
73 void __iomem *dir_clr;
74 };
75
76 /*
77 * GPIO names
78 */
79 static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
80 "p0.0", "p0.1", "p0.2", "p0.3",
81 "p0.4", "p0.5", "p0.6", "p0.7"
82 };
83
84 static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
85 "p1.0", "p1.1", "p1.2", "p1.3",
86 "p1.4", "p1.5", "p1.6", "p1.7",
87 "p1.8", "p1.9", "p1.10", "p1.11",
88 "p1.12", "p1.13", "p1.14", "p1.15",
89 "p1.16", "p1.17", "p1.18", "p1.19",
90 "p1.20", "p1.21", "p1.22", "p1.23",
91 };
92
93 static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
94 "p2.0", "p2.1", "p2.2", "p2.3",
95 "p2.4", "p2.5", "p2.6", "p2.7",
96 "p2.8", "p2.9", "p2.10", "p2.11",
97 "p2.12"
98 };
99
100 static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
101 "gpio00", "gpio01", "gpio02", "gpio03",
102 "gpio04", "gpio05"
103 };
104
105 static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
106 "gpi00", "gpi01", "gpi02", "gpi03",
107 "gpi04", "gpi05", "gpi06", "gpi07",
108 "gpi08", "gpi09", NULL, NULL,
109 NULL, NULL, NULL, "gpi15",
110 "gpi16", "gpi17", "gpi18", "gpi19",
111 "gpi20", "gpi21", "gpi22", "gpi23",
112 "gpi24", "gpi25", "gpi26", "gpi27"
113 };
114
115 static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
116 "gpo00", "gpo01", "gpo02", "gpo03",
117 "gpo04", "gpo05", "gpo06", "gpo07",
118 "gpo08", "gpo09", "gpo10", "gpo11",
119 "gpo12", "gpo13", "gpo14", "gpo15",
120 "gpo16", "gpo17", "gpo18", "gpo19",
121 "gpo20", "gpo21", "gpo22", "gpo23"
122 };
123
124 static struct gpio_regs gpio_grp_regs_p0 = {
125 .inp_state = LPC32XX_GPIO_P0_INP_STATE,
126 .outp_set = LPC32XX_GPIO_P0_OUTP_SET,
127 .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR,
128 .dir_set = LPC32XX_GPIO_P0_DIR_SET,
129 .dir_clr = LPC32XX_GPIO_P0_DIR_CLR,
130 };
131
132 static struct gpio_regs gpio_grp_regs_p1 = {
133 .inp_state = LPC32XX_GPIO_P1_INP_STATE,
134 .outp_set = LPC32XX_GPIO_P1_OUTP_SET,
135 .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR,
136 .dir_set = LPC32XX_GPIO_P1_DIR_SET,
137 .dir_clr = LPC32XX_GPIO_P1_DIR_CLR,
138 };
139
140 static struct gpio_regs gpio_grp_regs_p2 = {
141 .inp_state = LPC32XX_GPIO_P2_INP_STATE,
142 .outp_set = LPC32XX_GPIO_P2_OUTP_SET,
143 .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR,
144 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
145 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
146 };
147
148 static struct gpio_regs gpio_grp_regs_p3 = {
149 .inp_state = LPC32XX_GPIO_P3_INP_STATE,
150 .outp_state = LPC32XX_GPIO_P3_OUTP_STATE,
151 .outp_set = LPC32XX_GPIO_P3_OUTP_SET,
152 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
153 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
154 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
155 };
156
157 struct lpc32xx_gpio_chip {
158 struct gpio_chip chip;
159 struct gpio_regs *gpio_grp;
160 };
161
to_lpc32xx_gpio(struct gpio_chip * gpc)162 static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio(
163 struct gpio_chip *gpc)
164 {
165 return container_of(gpc, struct lpc32xx_gpio_chip, chip);
166 }
167
__set_gpio_dir_p012(struct lpc32xx_gpio_chip * group,unsigned pin,int input)168 static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
169 unsigned pin, int input)
170 {
171 if (input)
172 __raw_writel(GPIO012_PIN_TO_BIT(pin),
173 group->gpio_grp->dir_clr);
174 else
175 __raw_writel(GPIO012_PIN_TO_BIT(pin),
176 group->gpio_grp->dir_set);
177 }
178
__set_gpio_dir_p3(struct lpc32xx_gpio_chip * group,unsigned pin,int input)179 static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
180 unsigned pin, int input)
181 {
182 u32 u = GPIO3_PIN_TO_BIT(pin);
183
184 if (input)
185 __raw_writel(u, group->gpio_grp->dir_clr);
186 else
187 __raw_writel(u, group->gpio_grp->dir_set);
188 }
189
__set_gpio_level_p012(struct lpc32xx_gpio_chip * group,unsigned pin,int high)190 static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
191 unsigned pin, int high)
192 {
193 if (high)
194 __raw_writel(GPIO012_PIN_TO_BIT(pin),
195 group->gpio_grp->outp_set);
196 else
197 __raw_writel(GPIO012_PIN_TO_BIT(pin),
198 group->gpio_grp->outp_clr);
199 }
200
__set_gpio_level_p3(struct lpc32xx_gpio_chip * group,unsigned pin,int high)201 static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
202 unsigned pin, int high)
203 {
204 u32 u = GPIO3_PIN_TO_BIT(pin);
205
206 if (high)
207 __raw_writel(u, group->gpio_grp->outp_set);
208 else
209 __raw_writel(u, group->gpio_grp->outp_clr);
210 }
211
__set_gpo_level_p3(struct lpc32xx_gpio_chip * group,unsigned pin,int high)212 static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
213 unsigned pin, int high)
214 {
215 if (high)
216 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
217 else
218 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
219 }
220
__get_gpio_state_p012(struct lpc32xx_gpio_chip * group,unsigned pin)221 static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
222 unsigned pin)
223 {
224 return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
225 pin);
226 }
227
__get_gpio_state_p3(struct lpc32xx_gpio_chip * group,unsigned pin)228 static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
229 unsigned pin)
230 {
231 int state = __raw_readl(group->gpio_grp->inp_state);
232
233 /*
234 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
235 * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
236 */
237 return GPIO3_PIN_IN_SEL(state, pin);
238 }
239
__get_gpi_state_p3(struct lpc32xx_gpio_chip * group,unsigned pin)240 static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
241 unsigned pin)
242 {
243 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
244 }
245
__get_gpo_state_p3(struct lpc32xx_gpio_chip * group,unsigned pin)246 static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
247 unsigned pin)
248 {
249 return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
250 }
251
252 /*
253 * GENERIC_GPIO primitives.
254 */
lpc32xx_gpio_dir_input_p012(struct gpio_chip * chip,unsigned pin)255 static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
256 unsigned pin)
257 {
258 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
259
260 __set_gpio_dir_p012(group, pin, 1);
261
262 return 0;
263 }
264
lpc32xx_gpio_dir_input_p3(struct gpio_chip * chip,unsigned pin)265 static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
266 unsigned pin)
267 {
268 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
269
270 __set_gpio_dir_p3(group, pin, 1);
271
272 return 0;
273 }
274
lpc32xx_gpio_dir_in_always(struct gpio_chip * chip,unsigned pin)275 static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
276 unsigned pin)
277 {
278 return 0;
279 }
280
lpc32xx_gpio_get_value_p012(struct gpio_chip * chip,unsigned pin)281 static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
282 {
283 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
284
285 return __get_gpio_state_p012(group, pin);
286 }
287
lpc32xx_gpio_get_value_p3(struct gpio_chip * chip,unsigned pin)288 static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
289 {
290 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
291
292 return __get_gpio_state_p3(group, pin);
293 }
294
lpc32xx_gpi_get_value(struct gpio_chip * chip,unsigned pin)295 static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
296 {
297 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
298
299 return __get_gpi_state_p3(group, pin);
300 }
301
lpc32xx_gpio_dir_output_p012(struct gpio_chip * chip,unsigned pin,int value)302 static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
303 int value)
304 {
305 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
306
307 __set_gpio_level_p012(group, pin, value);
308 __set_gpio_dir_p012(group, pin, 0);
309
310 return 0;
311 }
312
lpc32xx_gpio_dir_output_p3(struct gpio_chip * chip,unsigned pin,int value)313 static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
314 int value)
315 {
316 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
317
318 __set_gpio_level_p3(group, pin, value);
319 __set_gpio_dir_p3(group, pin, 0);
320
321 return 0;
322 }
323
lpc32xx_gpio_dir_out_always(struct gpio_chip * chip,unsigned pin,int value)324 static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
325 int value)
326 {
327 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
328
329 __set_gpo_level_p3(group, pin, value);
330 return 0;
331 }
332
lpc32xx_gpio_set_value_p012(struct gpio_chip * chip,unsigned pin,int value)333 static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
334 int value)
335 {
336 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
337
338 __set_gpio_level_p012(group, pin, value);
339 }
340
lpc32xx_gpio_set_value_p3(struct gpio_chip * chip,unsigned pin,int value)341 static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
342 int value)
343 {
344 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
345
346 __set_gpio_level_p3(group, pin, value);
347 }
348
lpc32xx_gpo_set_value(struct gpio_chip * chip,unsigned pin,int value)349 static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
350 int value)
351 {
352 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
353
354 __set_gpo_level_p3(group, pin, value);
355 }
356
lpc32xx_gpo_get_value(struct gpio_chip * chip,unsigned pin)357 static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
358 {
359 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
360
361 return __get_gpo_state_p3(group, pin);
362 }
363
lpc32xx_gpio_request(struct gpio_chip * chip,unsigned pin)364 static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
365 {
366 if (pin < chip->ngpio)
367 return 0;
368
369 return -EINVAL;
370 }
371
372 static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
373 {
374 .chip = {
375 .label = "gpio_p0",
376 .direction_input = lpc32xx_gpio_dir_input_p012,
377 .get = lpc32xx_gpio_get_value_p012,
378 .direction_output = lpc32xx_gpio_dir_output_p012,
379 .set = lpc32xx_gpio_set_value_p012,
380 .request = lpc32xx_gpio_request,
381 .base = LPC32XX_GPIO_P0_GRP,
382 .ngpio = LPC32XX_GPIO_P0_MAX,
383 .names = gpio_p0_names,
384 .can_sleep = 0,
385 },
386 .gpio_grp = &gpio_grp_regs_p0,
387 },
388 {
389 .chip = {
390 .label = "gpio_p1",
391 .direction_input = lpc32xx_gpio_dir_input_p012,
392 .get = lpc32xx_gpio_get_value_p012,
393 .direction_output = lpc32xx_gpio_dir_output_p012,
394 .set = lpc32xx_gpio_set_value_p012,
395 .request = lpc32xx_gpio_request,
396 .base = LPC32XX_GPIO_P1_GRP,
397 .ngpio = LPC32XX_GPIO_P1_MAX,
398 .names = gpio_p1_names,
399 .can_sleep = 0,
400 },
401 .gpio_grp = &gpio_grp_regs_p1,
402 },
403 {
404 .chip = {
405 .label = "gpio_p2",
406 .direction_input = lpc32xx_gpio_dir_input_p012,
407 .get = lpc32xx_gpio_get_value_p012,
408 .direction_output = lpc32xx_gpio_dir_output_p012,
409 .set = lpc32xx_gpio_set_value_p012,
410 .request = lpc32xx_gpio_request,
411 .base = LPC32XX_GPIO_P2_GRP,
412 .ngpio = LPC32XX_GPIO_P2_MAX,
413 .names = gpio_p2_names,
414 .can_sleep = 0,
415 },
416 .gpio_grp = &gpio_grp_regs_p2,
417 },
418 {
419 .chip = {
420 .label = "gpio_p3",
421 .direction_input = lpc32xx_gpio_dir_input_p3,
422 .get = lpc32xx_gpio_get_value_p3,
423 .direction_output = lpc32xx_gpio_dir_output_p3,
424 .set = lpc32xx_gpio_set_value_p3,
425 .request = lpc32xx_gpio_request,
426 .base = LPC32XX_GPIO_P3_GRP,
427 .ngpio = LPC32XX_GPIO_P3_MAX,
428 .names = gpio_p3_names,
429 .can_sleep = 0,
430 },
431 .gpio_grp = &gpio_grp_regs_p3,
432 },
433 {
434 .chip = {
435 .label = "gpi_p3",
436 .direction_input = lpc32xx_gpio_dir_in_always,
437 .get = lpc32xx_gpi_get_value,
438 .request = lpc32xx_gpio_request,
439 .base = LPC32XX_GPI_P3_GRP,
440 .ngpio = LPC32XX_GPI_P3_MAX,
441 .names = gpi_p3_names,
442 .can_sleep = 0,
443 },
444 .gpio_grp = &gpio_grp_regs_p3,
445 },
446 {
447 .chip = {
448 .label = "gpo_p3",
449 .direction_output = lpc32xx_gpio_dir_out_always,
450 .set = lpc32xx_gpo_set_value,
451 .get = lpc32xx_gpo_get_value,
452 .request = lpc32xx_gpio_request,
453 .base = LPC32XX_GPO_P3_GRP,
454 .ngpio = LPC32XX_GPO_P3_MAX,
455 .names = gpo_p3_names,
456 .can_sleep = 0,
457 },
458 .gpio_grp = &gpio_grp_regs_p3,
459 },
460 };
461
lpc32xx_gpio_init(void)462 void __init lpc32xx_gpio_init(void)
463 {
464 int i;
465
466 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++)
467 gpiochip_add(&lpc32xx_gpiochip[i].chip);
468 }
469