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Searched refs:OUT_RING (Results 1 – 25 of 36) sorted by relevance

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/drivers/gpu/drm/nouveau/
Dnvc0_fbcon.c47 OUT_RING (chan, 1); in nvc0_fbcon_fillrect()
52 OUT_RING (chan, ((uint32_t *)info->pseudo_palette)[rect->color]); in nvc0_fbcon_fillrect()
54 OUT_RING (chan, rect->color); in nvc0_fbcon_fillrect()
56 OUT_RING (chan, rect->dx); in nvc0_fbcon_fillrect()
57 OUT_RING (chan, rect->dy); in nvc0_fbcon_fillrect()
58 OUT_RING (chan, rect->dx + rect->width); in nvc0_fbcon_fillrect()
59 OUT_RING (chan, rect->dy + rect->height); in nvc0_fbcon_fillrect()
62 OUT_RING (chan, 3); in nvc0_fbcon_fillrect()
82 OUT_RING (chan, 0); in nvc0_fbcon_copyarea()
84 OUT_RING (chan, region->dx); in nvc0_fbcon_copyarea()
[all …]
Dnv50_fbcon.c47 OUT_RING(chan, 1); in nv50_fbcon_fillrect()
52 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); in nv50_fbcon_fillrect()
54 OUT_RING(chan, rect->color); in nv50_fbcon_fillrect()
56 OUT_RING(chan, rect->dx); in nv50_fbcon_fillrect()
57 OUT_RING(chan, rect->dy); in nv50_fbcon_fillrect()
58 OUT_RING(chan, rect->dx + rect->width); in nv50_fbcon_fillrect()
59 OUT_RING(chan, rect->dy + rect->height); in nv50_fbcon_fillrect()
62 OUT_RING(chan, 3); in nv50_fbcon_fillrect()
82 OUT_RING(chan, 0); in nv50_fbcon_copyarea()
84 OUT_RING(chan, region->dx); in nv50_fbcon_copyarea()
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Dnv04_fbcon.c45 OUT_RING(chan, (region->sy << 16) | region->sx); in nv04_fbcon_copyarea()
46 OUT_RING(chan, (region->dy << 16) | region->dx); in nv04_fbcon_copyarea()
47 OUT_RING(chan, (region->height << 16) | region->width); in nv04_fbcon_copyarea()
66 OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3); in nv04_fbcon_fillrect()
70 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); in nv04_fbcon_fillrect()
72 OUT_RING(chan, rect->color); in nv04_fbcon_fillrect()
74 OUT_RING(chan, (rect->dx << 16) | rect->dy); in nv04_fbcon_fillrect()
75 OUT_RING(chan, (rect->width << 16) | rect->height); in nv04_fbcon_fillrect()
114 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff)); in nv04_fbcon_imageblit()
115 OUT_RING(chan, ((image->dy + image->height) << 16) | in nv04_fbcon_imageblit()
[all …]
Dnv50_display.c144 OUT_RING (evo, 0x80000000); in nv50_display_sync()
146 OUT_RING (evo, 0); in nv50_display_sync()
148 OUT_RING (evo, 0x00000000); in nv50_display_sync()
271 OUT_RING (evo, NV50_EVO_UNK84_NOTIFY_DISABLED); in nv50_display_init()
272 OUT_RING (evo, NvEvoSync); in nv50_display_init()
296 OUT_RING(evo, 0); in nv50_display_fini()
442 OUT_RING (evo, 0x00000000); in nv50_display_flip_stop()
444 OUT_RING (evo, 0x00000000); in nv50_display_flip_stop()
446 OUT_RING (evo, 0x00000000); in nv50_display_flip_stop()
448 OUT_RING (evo, 0x00000000); in nv50_display_flip_stop()
[all …]
Dnv50_crtc.c83 OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK); in nv50_crtc_blank()
84 OUT_RING(evo, 0); in nv50_crtc_blank()
87 OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE); in nv50_crtc_blank()
91 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE); in nv50_crtc_blank()
104 OUT_RING(evo, nv_crtc->lut.depth == 8 ? in nv50_crtc_blank()
107 OUT_RING(evo, nv_crtc->lut.nvbo->bo.offset >> 8); in nv50_crtc_blank()
110 OUT_RING(evo, NvEvoVRAM); in nv50_crtc_blank()
114 OUT_RING(evo, nv_crtc->fb.offset >> 8); in nv50_crtc_blank()
115 OUT_RING(evo, 0); in nv50_crtc_blank()
120 OUT_RING(evo, NvEvoFB32); in nv50_crtc_blank()
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Dnouveau_fence.c173 OUT_RING (chan, fence->sequence); in nouveau_fence_emit()
347 OUT_RING (chan, NvSema); in semaphore_acquire()
348 OUT_RING (chan, offset); in semaphore_acquire()
349 OUT_RING (chan, 1); in semaphore_acquire()
357 OUT_RING (chan, chan->vram_handle); in semaphore_acquire()
359 OUT_RING (chan, upper_32_bits(offset)); in semaphore_acquire()
360 OUT_RING (chan, lower_32_bits(offset)); in semaphore_acquire()
361 OUT_RING (chan, 1); in semaphore_acquire()
362 OUT_RING (chan, 1); /* ACQUIRE_EQ */ in semaphore_acquire()
369 OUT_RING (chan, upper_32_bits(offset)); in semaphore_acquire()
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Dnouveau_bo.c505 OUT_RING (chan, upper_32_bits(dst_offset)); in nvc0_bo_move_m2mf()
506 OUT_RING (chan, lower_32_bits(dst_offset)); in nvc0_bo_move_m2mf()
508 OUT_RING (chan, upper_32_bits(src_offset)); in nvc0_bo_move_m2mf()
509 OUT_RING (chan, lower_32_bits(src_offset)); in nvc0_bo_move_m2mf()
510 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ in nvc0_bo_move_m2mf()
511 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ in nvc0_bo_move_m2mf()
512 OUT_RING (chan, PAGE_SIZE); /* line_length */ in nvc0_bo_move_m2mf()
513 OUT_RING (chan, line_count); in nvc0_bo_move_m2mf()
515 OUT_RING (chan, 0x00100110); in nvc0_bo_move_m2mf()
550 OUT_RING (chan, 0); in nv50_bo_move_m2mf()
[all …]
Dnv50_cursor.c57 OUT_RING(evo, NvEvoVRAM); in nv50_cursor_show()
60 OUT_RING(evo, NV50_EVO_CRTC_CURSOR_CTRL_SHOW); in nv50_cursor_show()
61 OUT_RING(evo, nv_crtc->cursor.offset >> 8); in nv50_cursor_show()
65 OUT_RING(evo, 0); in nv50_cursor_show()
90 OUT_RING(evo, NV50_EVO_CRTC_CURSOR_CTRL_HIDE); in nv50_cursor_hide()
91 OUT_RING(evo, 0); in nv50_cursor_hide()
94 OUT_RING(evo, NV84_EVO_CRTC_CURSOR_DMA_HANDLE_NONE); in nv50_cursor_hide()
99 OUT_RING(evo, 0); in nv50_cursor_hide()
Dnouveau_dma.h116 OUT_RING(struct nouveau_channel *chan, int data) in OUT_RING() function
132 OUT_RING(chan, (op << 28) | (size << 16) | (subc << 13) | (mthd >> 2)); in BEGIN_NVC0()
138 OUT_RING(chan, (subc << 13) | (size << 18) | mthd); in BEGIN_RING()
Dnv50_dac.c59 OUT_RING (evo, 0); in nv50_dac_disconnect()
61 OUT_RING (evo, 0); in nv50_dac_disconnect()
244 OUT_RING(evo, mode_ctl); in nv50_dac_mode_set()
245 OUT_RING(evo, mode_ctl2); in nv50_dac_mode_set()
Dnouveau_fbcon.c175 OUT_RING (chan, 0); in nouveau_fbcon_sync()
177 OUT_RING (chan, 0); in nouveau_fbcon_sync()
180 OUT_RING (chan, 0); in nouveau_fbcon_sync()
182 OUT_RING (chan, 0); in nouveau_fbcon_sync()
Dnouveau_gem.c733 OUT_RING(chan, ((mem->start << PAGE_SHIFT) + in nouveau_gem_ioctl_pushbuf()
735 OUT_RING(chan, 0); in nouveau_gem_ioctl_pushbuf()
769 OUT_RING(chan, ((mem->start << PAGE_SHIFT) + in nouveau_gem_ioctl_pushbuf()
771 OUT_RING(chan, 0); in nouveau_gem_ioctl_pushbuf()
773 OUT_RING(chan, 0); in nouveau_gem_ioctl_pushbuf()
Dnv50_sor.c246 OUT_RING (evo, 0); in nv50_sor_disconnect()
248 OUT_RING (evo, 0); in nv50_sor_disconnect()
434 OUT_RING(evo, mode_ctl); in nv50_sor_mode_set()
Dnouveau_display.c450 OUT_RING (chan, 0x00000000); in nouveau_page_flip_emit()
451 OUT_RING (chan, 0x00000000); in nouveau_page_flip_emit()
454 OUT_RING (chan, ++chan->fence.sequence); in nouveau_page_flip_emit()
/drivers/gpu/drm/radeon/
Dr600_blit.c63 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); in set_render_target()
64 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); in set_render_target()
65 OUT_RING(gpu_addr >> 8); in set_render_target()
66 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0)); in set_render_target()
67 OUT_RING(2 << 0); in set_render_target()
70 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); in set_render_target()
71 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); in set_render_target()
72 OUT_RING(gpu_addr >> 8); in set_render_target()
75 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); in set_render_target()
76 OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2); in set_render_target()
[all …]
Dradeon_state.c458 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); in radeon_emit_clip_rect()
459 OUT_RING((box->y1 << 16) | box->x1); in radeon_emit_clip_rect()
460 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); in radeon_emit_clip_rect()
461 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1)); in radeon_emit_clip_rect()
490 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); in radeon_emit_state()
491 OUT_RING(ctx->pp_misc); in radeon_emit_state()
492 OUT_RING(ctx->pp_fog_color); in radeon_emit_state()
493 OUT_RING(ctx->re_solid_color); in radeon_emit_state()
494 OUT_RING(ctx->rb3d_blendcntl); in radeon_emit_state()
495 OUT_RING(ctx->rb3d_depthoffset); in radeon_emit_state()
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Dr300_cmdbuf.c74 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); in r300_emit_cliprects()
106 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) | in r300_emit_cliprects()
108 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) | in r300_emit_cliprects()
120 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1)); in r300_emit_cliprects()
121 OUT_RING(0); in r300_emit_cliprects()
122 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK); in r300_emit_cliprects()
147 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r300_emit_cliprects()
148 OUT_RING(R300_RB3D_DC_FLUSH); in r300_emit_cliprects()
151 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); in r300_emit_cliprects()
152 OUT_RING(RADEON_WAIT_3D_IDLECLEAN); in r300_emit_cliprects()
[all …]
Dradeon_drv.h1933 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1934 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1939 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1940 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1945 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1946 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1952 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1953 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1958 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1959 OUT_RING(RADEON_RB3D_DC_FLUSH); \
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Dr600_cp.c2317 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); in r600_do_cp_idle()
2318 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); in r600_do_cp_idle()
2320 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); in r600_do_cp_idle()
2321 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); in r600_do_cp_idle()
2322 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); in r600_do_cp_idle()
2339 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); in r600_do_cp_start()
2340 OUT_RING(0x00000001); in r600_do_cp_start()
2342 OUT_RING(0x00000003); in r600_do_cp_start()
2344 OUT_RING(0x00000000); in r600_do_cp_start()
2345 OUT_RING((dev_priv->r600_max_hw_contexts - 1)); in r600_do_cp_start()
[all …]
/drivers/gpu/drm/r128/
Dr128_state.c50 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3)); in r128_emit_clip_rects()
51 OUT_RING(boxes[0].x1); in r128_emit_clip_rects()
52 OUT_RING(boxes[0].x2 - 1); in r128_emit_clip_rects()
53 OUT_RING(boxes[0].y1); in r128_emit_clip_rects()
54 OUT_RING(boxes[0].y2 - 1); in r128_emit_clip_rects()
59 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3)); in r128_emit_clip_rects()
60 OUT_RING(boxes[1].x1); in r128_emit_clip_rects()
61 OUT_RING(boxes[1].x2 - 1); in r128_emit_clip_rects()
62 OUT_RING(boxes[1].y1); in r128_emit_clip_rects()
63 OUT_RING(boxes[1].y2 - 1); in r128_emit_clip_rects()
[all …]
Dr128_drv.h463 OUT_RING(CCE_PACKET0(R128_WAIT_UNTIL, 0)); \
464 OUT_RING(R128_EVENT_CRTC_OFFSET); \
522 #define OUT_RING(x) do { \ macro
/drivers/gpu/drm/i810/
Di810_dma.c467 OUT_RING(GFX_OP_COLOR_FACTOR); in i810EmitContextVerified()
468 OUT_RING(code[I810_CTXREG_CF1]); in i810EmitContextVerified()
470 OUT_RING(GFX_OP_STIPPLE); in i810EmitContextVerified()
471 OUT_RING(code[I810_CTXREG_ST1]); in i810EmitContextVerified()
478 OUT_RING(tmp); in i810EmitContextVerified()
485 OUT_RING(0); in i810EmitContextVerified()
499 OUT_RING(GFX_OP_MAP_INFO); in i810EmitTexVerified()
500 OUT_RING(code[I810_TEXREG_MI1]); in i810EmitTexVerified()
501 OUT_RING(code[I810_TEXREG_MI2]); in i810EmitTexVerified()
502 OUT_RING(code[I810_TEXREG_MI3]); in i810EmitTexVerified()
[all …]
/drivers/gpu/drm/i915/
Di915_dma.c344 OUT_RING(buffer[i]); in i915_emit_cmds()
346 OUT_RING(0); in i915_emit_cmds()
373 OUT_RING(GFX_OP_DRAWRECT_INFO_I965); in i915_emit_box()
374 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); in i915_emit_box()
375 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); in i915_emit_box()
376 OUT_RING(DR4); in i915_emit_box()
382 OUT_RING(GFX_OP_DRAWRECT_INFO); in i915_emit_box()
383 OUT_RING(DR1); in i915_emit_box()
384 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); in i915_emit_box()
385 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); in i915_emit_box()
[all …]
Dintel_overlay.c315 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON); in intel_overlay_on()
316 OUT_RING(overlay->flip_addr | OFC_UPDATE); in intel_overlay_on()
317 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); in intel_overlay_on()
318 OUT_RING(MI_NOOP); in intel_overlay_on()
359 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); in intel_overlay_continue()
360 OUT_RING(flip_addr); in intel_overlay_continue()
426 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); in intel_overlay_off()
427 OUT_RING(flip_addr); in intel_overlay_off()
428 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); in intel_overlay_off()
433 OUT_RING(MI_NOOP); in intel_overlay_off()
[all …]
/drivers/video/intelfb/
Dintelfbhw.c1553 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE); in do_flush()
1554 OUT_RING(MI_NOOP); in do_flush()
1691 OUT_RING(br00); in intelfbhw_do_fillrect()
1692 OUT_RING(br13); in intelfbhw_do_fillrect()
1693 OUT_RING(br14); in intelfbhw_do_fillrect()
1694 OUT_RING(br09); in intelfbhw_do_fillrect()
1695 OUT_RING(br16); in intelfbhw_do_fillrect()
1696 OUT_RING(MI_NOOP); in intelfbhw_do_fillrect()
1740 OUT_RING(br00); in intelfbhw_do_bitblt()
1741 OUT_RING(br13); in intelfbhw_do_bitblt()
[all …]

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