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Searched refs:PCH_DPLL_SEL (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_display.c841 pch_dpll = I915_READ(PCH_DPLL_SEL); in assert_pch_pll()
1272 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel) in intel_disable_pch_pll()
2982 temp = I915_READ(PCH_DPLL_SEL); in ironlake_pch_enable()
2993 I915_WRITE(PCH_DPLL_SEL, temp); in ironlake_pch_enable()
3179 temp = I915_READ(PCH_DPLL_SEL); in ironlake_crtc_disable()
3194 I915_WRITE(PCH_DPLL_SEL, temp); in ironlake_crtc_disable()
Di915_reg.h3315 #define PCH_DPLL_SEL 0xc7000 macro