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Searched refs:PPBUF_BASE2 (Results 1 – 14 of 14) sorted by relevance

/drivers/staging/rts_pstor/
Dms.h153 #define HEADER_ID0 PPBUF_BASE2
154 #define HEADER_ID1 (PPBUF_BASE2 + 1)
155 #define DISABLED_BLOCK0 (PPBUF_BASE2 + 0x170 + 4)
156 #define DISABLED_BLOCK1 (PPBUF_BASE2 + 0x170 + 5)
157 #define DISABLED_BLOCK2 (PPBUF_BASE2 + 0x170 + 6)
158 #define DISABLED_BLOCK3 (PPBUF_BASE2 + 0x170 + 7)
159 #define BLOCK_SIZE_0 (PPBUF_BASE2 + 0x1a0 + 2)
160 #define BLOCK_SIZE_1 (PPBUF_BASE2 + 0x1a0 + 3)
161 #define BLOCK_COUNT_0 (PPBUF_BASE2 + 0x1a0 + 4)
162 #define BLOCK_COUNT_1 (PPBUF_BASE2 + 0x1a0 + 5)
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Dms.c184 PPBUF_BASE2 + i, 0xFF, data[i]); in ms_write_bytes()
187 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF); in ms_write_bytes()
256 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0); in ms_read_bytes()
259 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0); in ms_read_bytes()
261 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1, 0, 0); in ms_read_bytes()
570 RTSX_READ_REG(chip, PPBUF_BASE2 + 2, &val); in ms_identify_media_type()
579 RTSX_READ_REG(chip, PPBUF_BASE2 + 4, &val); in ms_identify_media_type()
586 RTSX_READ_REG(chip, PPBUF_BASE2 + 5, &val); in ms_identify_media_type()
589 RTSX_READ_REG(chip, PPBUF_BASE2, &val); in ms_identify_media_type()
604 RTSX_READ_REG(chip, PPBUF_BASE2 + 3, &val); in ms_identify_media_type()
[all …]
Dsd.c191 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) { in sd_send_cmd_get_rsp()
2732 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0); in mmc_test_switch_bus()
2734 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0); in mmc_test_switch_bus()
2813 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0); in mmc_switch_timing_bus()
2814 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0); in mmc_switch_timing_bus()
2815 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0); in mmc_switch_timing_bus()
2816 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0); in mmc_switch_timing_bus()
2817 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0); in mmc_switch_timing_bus()
3666 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) { in ext_sd_send_cmd_get_rsp()
3776 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) { in ext_sd_get_rsp()
[all …]
Dspi.c603 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, buf[0]); in spi_write_flash()
643 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, buf[0]); in spi_write_flash()
799 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, status); in spi_write_flash_status()
Drtsx_card.h987 #define PPBUF_BASE2 0xFA00 macro
Drtsx_chip.c2194 reg_addr = PPBUF_BASE2; in rtsx_read_ppbuf()
2239 reg_addr = PPBUF_BASE2; in rtsx_write_ppbuf()
Dxd.c181 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, 0, 0); in xd_read_data_from_ppb()
/drivers/staging/rts5139/
Dms.h173 #define HEADER_ID0 (PPBUF_BASE2) /* 0 */
174 #define HEADER_ID1 (PPBUF_BASE2 + 1) /* 1 */
176 #define DISABLED_BLOCK0 (PPBUF_BASE2 + 0x170 + 4) /* 2 */
177 #define DISABLED_BLOCK1 (PPBUF_BASE2 + 0x170 + 5) /* 3 */
178 #define DISABLED_BLOCK2 (PPBUF_BASE2 + 0x170 + 6) /* 4 */
179 #define DISABLED_BLOCK3 (PPBUF_BASE2 + 0x170 + 7) /* 5 */
181 #define BLOCK_SIZE_0 (PPBUF_BASE2 + 0x1a0 + 2) /* 6 */
182 #define BLOCK_SIZE_1 (PPBUF_BASE2 + 0x1a0 + 3) /* 7 */
183 #define BLOCK_COUNT_0 (PPBUF_BASE2 + 0x1a0 + 4) /* 8 */
184 #define BLOCK_COUNT_1 (PPBUF_BASE2 + 0x1a0 + 5) /* 9 */
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Dsd_cprm.c123 for (reg_addr = PPBUF_BASE2;
124 reg_addr < PPBUF_BASE2 + 16; reg_addr++) {
171 reg_addr = PPBUF_BASE2;
247 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
704 (u16) (PPBUF_BASE2 + i), 0xFF,
716 (u16) (PPBUF_BASE2 + i), 0xFF,
728 (u16) (PPBUF_BASE2 + i), 0xFF,
Dms.c209 rts51x_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, in ms_write_bytes()
213 rts51x_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, in ms_write_bytes()
292 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0); in ms_read_bytes()
295 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, in ms_read_bytes()
298 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1, in ms_read_bytes()
456 rts51x_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, in ms_auto_set_cmd()
667 RTS51X_READ_REG(chip, PPBUF_BASE2 + 2, &val); in ms_identify_media_type()
675 RTS51X_READ_REG(chip, PPBUF_BASE2 + 4, &val); in ms_identify_media_type()
682 RTS51X_READ_REG(chip, PPBUF_BASE2 + 5, &val); in ms_identify_media_type()
685 RTS51X_READ_REG(chip, PPBUF_BASE2, &val); in ms_identify_media_type()
[all …]
Dsd.c143 for (reg_addr = PPBUF_BASE2;
144 reg_addr < PPBUF_BASE2 + 16; reg_addr++) {
206 reg_addr = PPBUF_BASE2;
2460 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0);
2463 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0);
2558 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0);
2559 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0);
2560 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0);
2561 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0);
2562 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0);
Drts51x_chip.c731 rts51x_seq_read_register(chip, PPBUF_BASE2, (u16) buf_len, buf); in rts51x_read_ppbuf()
746 rts51x_seq_write_register(chip, PPBUF_BASE2, (u16) buf_len, buf); in rts51x_write_ppbuf()
Drts51x_card.h736 #define PPBUF_BASE2 0xFA00 macro
Dxd.c218 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, 0, in xd_read_data_from_ppb()