Searched refs:PSB_RVDC32 (Results 1 – 7 of 7) sorted by relevance
194 regs->psb.saveDSPARB = PSB_RVDC32(DSPARB); in oaktrail_save_display_registers()195 regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1); in oaktrail_save_display_registers()196 regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2); in oaktrail_save_display_registers()197 regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3); in oaktrail_save_display_registers()198 regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4); in oaktrail_save_display_registers()199 regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5); in oaktrail_save_display_registers()200 regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6); in oaktrail_save_display_registers()201 regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT); in oaktrail_save_display_registers()204 regs->psb.savePIPEACONF = PSB_RVDC32(PIPEACONF); in oaktrail_save_display_registers()205 regs->psb.savePIPEASRC = PSB_RVDC32(PIPEASRC); in oaktrail_save_display_registers()[all …]
446 hdmi_dev->saveDPLL_CTRL = PSB_RVDC32(DPLL_CTRL); in oaktrail_hdmi_save()447 hdmi_dev->saveDPLL_DIV_CTRL = PSB_RVDC32(DPLL_DIV_CTRL); in oaktrail_hdmi_save()448 hdmi_dev->saveDPLL_ADJUST = PSB_RVDC32(DPLL_ADJUST); in oaktrail_hdmi_save()449 hdmi_dev->saveDPLL_UPDATE = PSB_RVDC32(DPLL_UPDATE); in oaktrail_hdmi_save()450 hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE); in oaktrail_hdmi_save()453 regs->savePIPEBCONF = PSB_RVDC32(PIPEBCONF); in oaktrail_hdmi_save()454 regs->savePIPEBSRC = PSB_RVDC32(PIPEBSRC); in oaktrail_hdmi_save()455 regs->saveHTOTAL_B = PSB_RVDC32(HTOTAL_B); in oaktrail_hdmi_save()456 regs->saveHBLANK_B = PSB_RVDC32(HBLANK_B); in oaktrail_hdmi_save()457 regs->saveHSYNC_B = PSB_RVDC32(HSYNC_B); in oaktrail_hdmi_save()[all …]
309 *dpll_val = PSB_RVDC32(dpll_reg); in mdfld_save_display_registers()310 *fp_val = PSB_RVDC32(fp_reg); in mdfld_save_display_registers()311 *pipeconf_val = PSB_RVDC32(pipeconf_reg); in mdfld_save_display_registers()312 *htot_val = PSB_RVDC32(htot_reg); in mdfld_save_display_registers()313 *hblank_val = PSB_RVDC32(hblank_reg); in mdfld_save_display_registers()314 *hsync_val = PSB_RVDC32(hsync_reg); in mdfld_save_display_registers()315 *vtot_val = PSB_RVDC32(vtot_reg); in mdfld_save_display_registers()316 *vblank_val = PSB_RVDC32(vblank_reg); in mdfld_save_display_registers()317 *vsync_val = PSB_RVDC32(vsync_reg); in mdfld_save_display_registers()318 *pipesrc_val = PSB_RVDC32(pipesrc_reg); in mdfld_save_display_registers()[all …]
93 u32 writeVal = PSB_RVDC32(reg); in psb_enable_pipestat()96 (void) PSB_RVDC32(reg); in psb_enable_pipestat()109 u32 writeVal = PSB_RVDC32(reg); in psb_disable_pipestat()112 (void) PSB_RVDC32(reg); in psb_disable_pipestat()160 pipe_stat_val = PSB_RVDC32(pipe_stat_reg); in mid_pipe_event_handler()169 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg); in mid_pipe_event_handler()170 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status; in mid_pipe_event_handler()179 __func__, pipe, PSB_RVDC32(pipe_stat_reg)); in mid_pipe_event_handler()211 vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R); in psb_irq_handler()245 (void) PSB_RVDC32(PSB_INT_IDENTITY_R); in psb_irq_handler()[all …]
183 regs->saveDSPARB = PSB_RVDC32(DSPARB); in psb_save_display_registers()184 regs->saveDSPFW1 = PSB_RVDC32(DSPFW1); in psb_save_display_registers()185 regs->saveDSPFW2 = PSB_RVDC32(DSPFW2); in psb_save_display_registers()186 regs->saveDSPFW3 = PSB_RVDC32(DSPFW3); in psb_save_display_registers()187 regs->saveDSPFW4 = PSB_RVDC32(DSPFW4); in psb_save_display_registers()188 regs->saveDSPFW5 = PSB_RVDC32(DSPFW5); in psb_save_display_registers()189 regs->saveDSPFW6 = PSB_RVDC32(DSPFW6); in psb_save_display_registers()190 regs->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT); in psb_save_display_registers()
399 (void) PSB_RVDC32(PSB_PGETBL_CTL); in psb_gtt_takedown()429 dev_priv->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL); in psb_gtt_init()431 (void) PSB_RVDC32(PSB_PGETBL_CTL); in psb_gtt_init()
969 #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs)) macro