Searched refs:RB_CTRL (Results 1 – 4 of 4) sorted by relevance
| /drivers/net/ethernet/marvell/ |
| D | sky2.c | 1053 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); in sky2_ramset()
1076 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); in sky2_ramset()
1079 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); in sky2_ramset()
1080 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); in sky2_ramset()
1345 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); in sky2_rx_stop()
1702 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), in sky2_hw_up()
2074 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); in sky2_tx_reset()
2093 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), in sky2_hw_down()
2449 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); in sky2_change_mtu()
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| D | skge.c | 2478 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); in skge_ramset()
2494 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); in skge_ramset()
2497 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); in skge_ramset()
2631 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), in skge_rx_stop()
2672 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), in skge_down()
2686 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); in skge_down()
2689 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); in skge_down()
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| D | skge.h | 497 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */ enumerator
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| D | sky2.h | 798 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */ enumerator
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