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Searched refs:REG_RD (Results 1 – 18 of 18) sorted by relevance

/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_main.c528 data[i] = REG_RD(bp, src_addr + i*4); in bnx2x_read_dmae()
601 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + in bnx2x_mc_assert()
603 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + in bnx2x_mc_assert()
605 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + in bnx2x_mc_assert()
607 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + in bnx2x_mc_assert()
628 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + in bnx2x_mc_assert()
630 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + in bnx2x_mc_assert()
632 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + in bnx2x_mc_assert()
634 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + in bnx2x_mc_assert()
655 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + in bnx2x_mc_assert()
[all …]
Dbnx2x_link.c309 u32 val = REG_RD(bp, reg); in bnx2x_bits_en()
318 u32 val = REG_RD(bp, reg); in bnx2x_bits_dis()
340 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); in bnx2x_get_epio()
343 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; in bnx2x_get_epio()
357 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); in bnx2x_set_epio()
366 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); in bnx2x_set_epio()
1417 val_xoff = REG_RD(bp, emac_base + in bnx2x_emac_get_pfc_stat()
1420 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); in bnx2x_emac_get_pfc_stat()
1426 val_xoff = REG_RD(bp, emac_base + in bnx2x_emac_get_pfc_stat()
1429 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); in bnx2x_emac_get_pfc_stat()
[all …]
Dbnx2x_init.h208 u32 curr_cos = REG_RD(bp, QM_REG_QVOQIDX_0 + q_num * 4); in bnx2x_map_q_cos()
235 reg_bit_map = REG_RD(bp, reg_addr); in bnx2x_map_q_cos()
240 reg_bit_map = REG_RD(bp, reg_addr); in bnx2x_map_q_cos()
247 reg_bit_map = REG_RD(bp, reg_addr); in bnx2x_map_q_cos()
459 reg_val = REG_RD(bp, mcp_attn_ctl_regs[i]); in bnx2x_set_mcp_parity()
524 reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i]. in bnx2x_clear_blocks_parity()
535 reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP); in bnx2x_clear_blocks_parity()
Dbnx2x_ethtool.c744 *p++ = REG_RD(bp, in bnx2x_read_pages_regs()
758 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); in __bnx2x_get_regs()
785 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR); in bnx2x_get_regs()
786 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR); in bnx2x_get_regs()
787 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR); in bnx2x_get_regs()
788 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR); in bnx2x_get_regs()
956 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); in bnx2x_acquire_nvram_lock()
988 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); in bnx2x_release_nvram_lock()
1010 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); in bnx2x_enable_nvram_access()
1022 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); in bnx2x_disable_nvram_access()
[all …]
Dbnx2x_init_ops.h260 REG_RD(bp, addr); in bnx2x_init_block()
516 val = REG_RD(bp, write_arb_addr[i].l); in bnx2x_init_pxp_arb()
520 val = REG_RD(bp, write_arb_addr[i].add); in bnx2x_init_pxp_arb()
524 val = REG_RD(bp, write_arb_addr[i].ubound); in bnx2x_init_pxp_arb()
585 val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST); in bnx2x_init_pxp_arb()
Dbnx2x.h147 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) macro
182 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
187 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
194 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
197 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
203 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
1752 val = REG_RD(bp, reg); in reg_poll()
Dbnx2x_cmn.h649 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) in bnx2x_igu_clear_sb_gen()
653 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { in bnx2x_igu_clear_sb_gen()
705 u32 result = REG_RD(bp, hc_addr); in bnx2x_hc_ack_int()
714 u32 result = REG_RD(bp, igu_addr); in bnx2x_igu_ack_int()
Dbnx2x_stats.c1470 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38); in bnx2x_stats_init()
1472 REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38); in bnx2x_stats_init()
Dbnx2x_dcb.c60 *buff = REG_RD(bp, addr + i); in bnx2x_read_data()
Dbnx2x_cmn.c1750 u32 loaded_fw = REG_RD(bp, XSEM_REG_PRAM); in bnx2x_test_firmware_version()
/drivers/net/ethernet/broadcom/
Dbnx2.c277 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW); in bnx2_reg_rd_ind()
315 val = REG_RD(bp, BNX2_CTX_CTX_CTRL); in bnx2_ctx_wr()
496 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); in bnx2_read_phy()
500 REG_RD(bp, BNX2_EMAC_MDIO_MODE); in bnx2_read_phy()
513 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); in bnx2_read_phy()
517 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); in bnx2_read_phy()
534 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); in bnx2_read_phy()
538 REG_RD(bp, BNX2_EMAC_MDIO_MODE); in bnx2_read_phy()
553 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); in bnx2_write_phy()
557 REG_RD(bp, BNX2_EMAC_MDIO_MODE); in bnx2_write_phy()
[all …]
Dbnx2.h6951 #define REG_RD(bp, offset) \ macro
/drivers/media/radio/wl128x/
Dfmdrv_rx.c83 ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, NULL, NULL); in fm_rx_set_freq()
115 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, 2, &curr_frq, &resp_len); in fm_rx_set_freq()
187 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, in fm_rx_seek()
227 ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, NULL, NULL); in fm_rx_seek()
283 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, 2, in fm_rx_seek()
529 ret = fmc_send_cmd(fmdev, RSSI_LVL_GET, REG_RD, NULL, 2, in fm_rx_get_rssi_level()
620 ret = fmc_send_cmd(fmdev, MOST_MODE_SET, REG_RD, NULL, 2, in fm_rx_get_stereo_mono()
700 ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, in fm_rx_set_rds_mode()
Dfmdrv_common.c580 if (!fm_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, sizeof(flag), NULL)) in fm_irq_send_flag_getcmd()
630 if (!fm_send_cmd(fmdev, RDS_DATA_GET, REG_RD, NULL, in fm_irq_send_rdsdata_getcmd()
976 if (!fm_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, sizeof(payload), NULL)) in fm_irq_afjump_rd_freq()
1343 if (fmc_send_cmd(fmdev, ASIC_ID_GET, REG_RD, NULL, in fm_power_up()
1347 if (fmc_send_cmd(fmdev, ASIC_VER_GET, REG_RD, NULL, in fm_power_up()
Dfmdrv_common.h28 #define REG_RD 0x1 macro
Dfmdrv_tx.c372 ret = fmc_send_cmd(fmdev, READ_FMANT_TUNE_VALUE, REG_RD, in fm_tx_get_tune_cap_val()
/drivers/scsi/bnx2i/
Dbnx2i.h124 #define REG_RD(__hba, offset) \ macro
Dbnx2i_hwi.c2733 config2 = REG_RD(ep->hba, BNX2_MQ_CONFIG2); in bnx2i_map_ep_dbell_regs()