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Searched refs:SD_CLK_DIVIDE_0 (Results 1 – 4 of 4) sorted by relevance

/drivers/staging/rts5139/
Drts51x_card.h309 #define SD_CLK_DIVIDE_0 0x00 macro
Dsd.c2245 RTS51X_WRITE_REG(chip, SD_CFG1, SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
2774 RTS51X_WRITE_REG(chip, SD_CFG1, SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
2941 SD_CLK_DIVIDE_0);
/drivers/staging/rts_pstor/
Drtsx_card.h159 #define SD_CLK_DIVIDE_0 0x00 macro
Dsd.c687 if (clk_div == SD_CLK_DIVIDE_0) { in sd_set_clock_divider()
2519 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); in reset_sd()
3023 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); in reset_mmc()
3171 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); in reset_sd_card()
3223 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); in reset_mmc_only()