• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  * This file is provided under a dual BSD/GPLv2 license.  When using or
3  * redistributing this file, you may do so under either license.
4  *
5  * GPL LICENSE SUMMARY
6  *
7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of version 2 of the GNU General Public License as
11  * published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16  * General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21  * The full GNU General Public License is included in this distribution
22  * in the file called LICENSE.GPL.
23  *
24  * BSD LICENSE
25  *
26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27  * All rights reserved.
28  *
29  * Redistribution and use in source and binary forms, with or without
30  * modification, are permitted provided that the following conditions
31  * are met:
32  *
33  *   * Redistributions of source code must retain the above copyright
34  *     notice, this list of conditions and the following disclaimer.
35  *   * Redistributions in binary form must reproduce the above copyright
36  *     notice, this list of conditions and the following disclaimer in
37  *     the documentation and/or other materials provided with the
38  *     distribution.
39  *   * Neither the name of Intel Corporation nor the names of its
40  *     contributors may be used to endorse or promote products derived
41  *     from this software without specific prior written permission.
42  *
43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54  */
55 
56 #ifndef _SCU_REGISTERS_H_
57 #define _SCU_REGISTERS_H_
58 
59 /**
60  * This file contains the constants and structures for the SCU memory mapped
61  *    registers.
62  *
63  *
64  */
65 
66 #define SCU_VIIT_ENTRY_ID_MASK         (0xC0000000)
67 #define SCU_VIIT_ENTRY_ID_SHIFT        (30)
68 
69 #define SCU_VIIT_ENTRY_FUNCTION_MASK   (0x0FF00000)
70 #define SCU_VIIT_ENTRY_FUNCTION_SHIFT  (20)
71 
72 #define SCU_VIIT_ENTRY_IPPTMODE_MASK   (0x0001F800)
73 #define SCU_VIIT_ENTRY_IPPTMODE_SHIFT  (12)
74 
75 #define SCU_VIIT_ENTRY_LPVIE_MASK      (0x00000F00)
76 #define SCU_VIIT_ENTRY_LPVIE_SHIFT     (8)
77 
78 #define SCU_VIIT_ENTRY_STATUS_MASK     (0x000000FF)
79 #define SCU_VIIT_ENTRY_STATUS_SHIFT    (0)
80 
81 #define SCU_VIIT_ENTRY_ID_INVALID   (0 << SCU_VIIT_ENTRY_ID_SHIFT)
82 #define SCU_VIIT_ENTRY_ID_VIIT      (1 << SCU_VIIT_ENTRY_ID_SHIFT)
83 #define SCU_VIIT_ENTRY_ID_IIT       (2 << SCU_VIIT_ENTRY_ID_SHIFT)
84 #define SCU_VIIT_ENTRY_ID_VIRT_EXP  (3 << SCU_VIIT_ENTRY_ID_SHIFT)
85 
86 #define SCU_VIIT_IPPT_SSP_INITIATOR (0x01 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
87 #define SCU_VIIT_IPPT_SMP_INITIATOR (0x02 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
88 #define SCU_VIIT_IPPT_STP_INITIATOR (0x04 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
89 #define SCU_VIIT_IPPT_INITIATOR	    \
90 	(\
91 		SCU_VIIT_IPPT_SSP_INITIATOR  \
92 		| SCU_VIIT_IPPT_SMP_INITIATOR  \
93 		| SCU_VIIT_IPPT_STP_INITIATOR  \
94 	)
95 
96 #define SCU_VIIT_STATUS_RNC_VALID      (0x01 << SCU_VIIT_ENTRY_STATUS_SHIFT)
97 #define SCU_VIIT_STATUS_ADDRESS_VALID  (0x02 << SCU_VIIT_ENTRY_STATUS_SHIFT)
98 #define SCU_VIIT_STATUS_RNI_VALID      (0x04 << SCU_VIIT_ENTRY_STATUS_SHIFT)
99 #define SCU_VIIT_STATUS_ALL_VALID      \
100 	(\
101 		SCU_VIIT_STATUS_RNC_VALID	\
102 		| SCU_VIIT_STATUS_ADDRESS_VALID	  \
103 		| SCU_VIIT_STATUS_RNI_VALID	  \
104 	)
105 
106 #define SCU_VIIT_IPPT_SMP_TARGET    (0x10 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
107 
108 /**
109  * struct scu_viit_entry - This is the SCU Virtual Initiator Table Entry
110  *
111  *
112  */
113 struct scu_viit_entry {
114 	/**
115 	 * This must be encoded as to the type of initiator that is being constructed
116 	 * for this port.
117 	 */
118 	u32 status;
119 
120 	/**
121 	 * Virtual initiator high SAS Address
122 	 */
123 	u32 initiator_sas_address_hi;
124 
125 	/**
126 	 * Virtual initiator low SAS Address
127 	 */
128 	u32 initiator_sas_address_lo;
129 
130 	/**
131 	 * This must be 0
132 	 */
133 	u32 reserved;
134 
135 };
136 
137 
138 /* IIT Status Defines */
139 #define SCU_IIT_ENTRY_ID_MASK                (0xC0000000)
140 #define SCU_IIT_ENTRY_ID_SHIFT               (30)
141 
142 #define SCU_IIT_ENTRY_STATUS_UPDATE_MASK     (0x20000000)
143 #define SCU_IIT_ENTRY_STATUS_UPDATE_SHIFT    (29)
144 
145 #define SCU_IIT_ENTRY_LPI_MASK               (0x00000F00)
146 #define SCU_IIT_ENTRY_LPI_SHIFT              (8)
147 
148 #define SCU_IIT_ENTRY_STATUS_MASK            (0x000000FF)
149 #define SCU_IIT_ENTRY_STATUS_SHIFT           (0)
150 
151 /* IIT Remote Initiator Defines */
152 #define SCU_IIT_ENTRY_REMOTE_TAG_MASK  (0x0000FFFF)
153 #define SCU_IIT_ENTRY_REMOTE_TAG_SHIFT (0)
154 
155 #define SCU_IIT_ENTRY_REMOTE_RNC_MASK  (0x0FFF0000)
156 #define SCU_IIT_ENTRY_REMOTE_RNC_SHIFT (16)
157 
158 #define SCU_IIT_ENTRY_ID_INVALID   (0 << SCU_IIT_ENTRY_ID_SHIFT)
159 #define SCU_IIT_ENTRY_ID_VIIT      (1 << SCU_IIT_ENTRY_ID_SHIFT)
160 #define SCU_IIT_ENTRY_ID_IIT       (2 << SCU_IIT_ENTRY_ID_SHIFT)
161 #define SCU_IIT_ENTRY_ID_VIRT_EXP  (3 << SCU_IIT_ENTRY_ID_SHIFT)
162 
163 /**
164  * struct scu_iit_entry - This will be implemented later when we support
165  *    virtual functions
166  *
167  *
168  */
169 struct scu_iit_entry {
170 	u32 status;
171 	u32 remote_initiator_sas_address_hi;
172 	u32 remote_initiator_sas_address_lo;
173 	u32 remote_initiator;
174 
175 };
176 
177 /* Generate a value for an SCU register */
178 #define SCU_GEN_VALUE(name, value) \
179 	(((value) << name ## _SHIFT) & (name ## _MASK))
180 
181 /*
182  * Generate a bit value for an SCU register
183  * Make sure that the register MASK is just a single bit */
184 #define SCU_GEN_BIT(name) \
185 	SCU_GEN_VALUE(name, ((u32)1))
186 
187 #define SCU_SET_BIT(name, reg_value) \
188 	((reg_value) | SCU_GEN_BIT(name))
189 
190 #define SCU_CLEAR_BIT(name, reg_value) \
191 	((reg_value)$ ~(SCU_GEN_BIT(name)))
192 
193 /*
194  * *****************************************************************************
195  * Unions for bitfield definitions of SCU Registers
196  * SMU Post Context Port
197  * ***************************************************************************** */
198 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_SHIFT         (0)
199 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_MASK          (0x00000FFF)
200 #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_SHIFT    (12)
201 #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_MASK     (0x0000F000)
202 #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_SHIFT       (16)
203 #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_MASK        (0x00030000)
204 #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_SHIFT       (18)
205 #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_MASK        (0x00FC0000)
206 #define SMU_POST_CONTEXT_PORT_RESERVED_MASK               (0xFF000000)
207 
208 #define SMU_PCP_GEN_VAL(name, value) \
209 	SCU_GEN_VALUE(SMU_POST_CONTEXT_PORT_ ## name, value)
210 
211 /* ***************************************************************************** */
212 #define SMU_INTERRUPT_STATUS_COMPLETION_SHIFT       (31)
213 #define SMU_INTERRUPT_STATUS_COMPLETION_MASK        (0x80000000)
214 #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_SHIFT    (1)
215 #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_MASK     (0x00000002)
216 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_SHIFT      (0)
217 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_MASK       (0x00000001)
218 #define SMU_INTERRUPT_STATUS_RESERVED_MASK          (0x7FFFFFFC)
219 
220 #define SMU_ISR_GEN_BIT(name) \
221 	SCU_GEN_BIT(SMU_INTERRUPT_STATUS_ ## name)
222 
223 #define SMU_ISR_QUEUE_ERROR   SMU_ISR_GEN_BIT(QUEUE_ERROR)
224 #define SMU_ISR_QUEUE_SUSPEND SMU_ISR_GEN_BIT(QUEUE_SUSPEND)
225 #define SMU_ISR_COMPLETION    SMU_ISR_GEN_BIT(COMPLETION)
226 
227 /* ***************************************************************************** */
228 #define SMU_INTERRUPT_MASK_COMPLETION_SHIFT         (31)
229 #define SMU_INTERRUPT_MASK_COMPLETION_MASK          (0x80000000)
230 #define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_SHIFT      (1)
231 #define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_MASK       (0x00000002)
232 #define SMU_INTERRUPT_MASK_QUEUE_ERROR_SHIFT        (0)
233 #define SMU_INTERRUPT_MASK_QUEUE_ERROR_MASK         (0x00000001)
234 #define SMU_INTERRUPT_MASK_RESERVED_MASK            (0x7FFFFFFC)
235 
236 #define SMU_IMR_GEN_BIT(name) \
237 	SCU_GEN_BIT(SMU_INTERRUPT_MASK_ ## name)
238 
239 #define SMU_IMR_QUEUE_ERROR   SMU_IMR_GEN_BIT(QUEUE_ERROR)
240 #define SMU_IMR_QUEUE_SUSPEND SMU_IMR_GEN_BIT(QUEUE_SUSPEND)
241 #define SMU_IMR_COMPLETION    SMU_IMR_GEN_BIT(COMPLETION)
242 
243 /* ***************************************************************************** */
244 #define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_SHIFT    (0)
245 #define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_MASK     (0x0000001F)
246 #define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_SHIFT   (8)
247 #define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_MASK    (0x0000FF00)
248 #define SMU_INTERRUPT_COALESCING_CONTROL_RESERVED_MASK  (0xFFFF00E0)
249 
250 #define SMU_ICC_GEN_VAL(name, value) \
251 	SCU_GEN_VALUE(SMU_INTERRUPT_COALESCING_CONTROL_ ## name, value)
252 
253 /* ***************************************************************************** */
254 #define SMU_TASK_CONTEXT_RANGE_START_SHIFT      (0)
255 #define SMU_TASK_CONTEXT_RANGE_START_MASK       (0x00000FFF)
256 #define SMU_TASK_CONTEXT_RANGE_ENDING_SHIFT     (16)
257 #define SMU_TASK_CONTEXT_RANGE_ENDING_MASK      (0x0FFF0000)
258 #define SMU_TASK_CONTEXT_RANGE_ENABLE_SHIFT     (31)
259 #define SMU_TASK_CONTEXT_RANGE_ENABLE_MASK      (0x80000000)
260 #define SMU_TASK_CONTEXT_RANGE_RESERVED_MASK    (0x7000F000)
261 
262 #define SMU_TCR_GEN_VAL(name, value) \
263 	SCU_GEN_VALUE(SMU_TASK_CONTEXT_RANGE_ ## name, value)
264 
265 #define SMU_TCR_GEN_BIT(name, value) \
266 	SCU_GEN_BIT(SMU_TASK_CONTEXT_RANGE_ ## name)
267 
268 /* ***************************************************************************** */
269 
270 #define SMU_COMPLETION_QUEUE_PUT_POINTER_SHIFT          (0)
271 #define SMU_COMPLETION_QUEUE_PUT_POINTER_MASK           (0x00003FFF)
272 #define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_SHIFT        (15)
273 #define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_MASK         (0x00008000)
274 #define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_SHIFT    (16)
275 #define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_MASK     (0x03FF0000)
276 #define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_SHIFT  (26)
277 #define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_MASK   (0x04000000)
278 #define SMU_COMPLETION_QUEUE_PUT_RESERVED_MASK          (0xF8004000)
279 
280 #define SMU_CQPR_GEN_VAL(name, value) \
281 	SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_PUT_ ## name, value)
282 
283 #define SMU_CQPR_GEN_BIT(name) \
284 	SCU_GEN_BIT(SMU_COMPLETION_QUEUE_PUT_ ## name)
285 
286 /* ***************************************************************************** */
287 
288 #define SMU_COMPLETION_QUEUE_GET_POINTER_SHIFT          (0)
289 #define SMU_COMPLETION_QUEUE_GET_POINTER_MASK           (0x00003FFF)
290 #define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT        (15)
291 #define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_MASK         (0x00008000)
292 #define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT    (16)
293 #define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK     (0x03FF0000)
294 #define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT  (26)
295 #define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_MASK   (0x04000000)
296 #define SMU_COMPLETION_QUEUE_GET_ENABLE_SHIFT           (30)
297 #define SMU_COMPLETION_QUEUE_GET_ENABLE_MASK            (0x40000000)
298 #define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_SHIFT     (31)
299 #define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_MASK      (0x80000000)
300 #define SMU_COMPLETION_QUEUE_GET_RESERVED_MASK          (0x38004000)
301 
302 #define SMU_CQGR_GEN_VAL(name, value) \
303 	SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_GET_ ## name, value)
304 
305 #define SMU_CQGR_GEN_BIT(name) \
306 	SCU_GEN_BIT(SMU_COMPLETION_QUEUE_GET_ ## name)
307 
308 #define SMU_CQGR_CYCLE_BIT \
309 	SMU_CQGR_GEN_BIT(CYCLE_BIT)
310 
311 #define SMU_CQGR_EVENT_CYCLE_BIT \
312 	SMU_CQGR_GEN_BIT(EVENT_CYCLE_BIT)
313 
314 #define SMU_CQGR_GET_POINTER_SET(value)	\
315 	SMU_CQGR_GEN_VAL(POINTER, value)
316 
317 
318 /* ***************************************************************************** */
319 #define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_SHIFT  (0)
320 #define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_MASK   (0x00003FFF)
321 #define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_SHIFT  (16)
322 #define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_MASK   (0x03FF0000)
323 #define SMU_COMPLETION_QUEUE_CONTROL_RESERVED_MASK      (0xFC00C000)
324 
325 #define SMU_CQC_GEN_VAL(name, value) \
326 	SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_CONTROL_ ## name, value)
327 
328 #define SMU_CQC_QUEUE_LIMIT_SET(value) \
329 	SMU_CQC_GEN_VAL(QUEUE_LIMIT, value)
330 
331 #define SMU_CQC_EVENT_LIMIT_SET(value) \
332 	SMU_CQC_GEN_VAL(EVENT_LIMIT, value)
333 
334 
335 /* ***************************************************************************** */
336 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT    (0)
337 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK     (0x00000FFF)
338 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT    (12)
339 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK     (0x00007000)
340 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT   (15)
341 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK    (0x07FF8000)
342 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_SHIFT   (27)
343 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK    (0x08000000)
344 #define SMU_DEVICE_CONTEXT_CAPACITY_RESERVED_MASK   (0xF0000000)
345 
346 #define SMU_DCC_GEN_VAL(name, value) \
347 	SCU_GEN_VALUE(SMU_DEVICE_CONTEXT_CAPACITY_ ## name, value)
348 
349 #define SMU_DCC_GET_MAX_PEG(value) \
350 	(\
351 		((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK) \
352 		>> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \
353 	)
354 
355 #define SMU_DCC_GET_MAX_LP(value) \
356 	(\
357 		((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
358 		>> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \
359 	)
360 
361 #define SMU_DCC_GET_MAX_TC(value) \
362 	(\
363 		((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
364 		>> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT \
365 	)
366 
367 #define SMU_DCC_GET_MAX_RNC(value) \
368 	(\
369 		((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
370 		>> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT \
371 	)
372 
373 /* ***************************************************************************** */
374 #define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_SHIFT    (0)
375 #define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_MASK     (0x00000001)
376 #define SMU_CLOCK_GATING_CONTROL_XCLK_ENABLE_SHIFT    (1)
377 #define SMU_CLOCK_GATING_CONTROL_XCLK_ENABLE_MASK     (0x00000002)
378 #define SMU_CLOCK_GATING_CONTROL_TXCLK_ENABLE_SHIFT   (2)
379 #define SMU_CLOCK_GATING_CONTROL_TXCLK_ENABLE_MASK    (0x00000004)
380 #define SMU_CLOCK_GATING_CONTROL_REGCLK_ENABLE_SHIFT  (3)
381 #define SMU_CLOCK_GATING_CONTROL_REGCLK_ENABLE_MASK   (0x00000008)
382 #define SMU_CLOCK_GATING_CONTROL_IDLE_TIMEOUT_SHIFT   (16)
383 #define SMU_CLOCK_GATING_CONTROL_IDLE_TIMEOUT_MASK    (0x000F0000)
384 #define SMU_CLOCK_GATING_CONTROL_FORCE_IDLE_SHIFT     (31)
385 #define SMU_CLOCK_GATING_CONTROL_FORCE_IDLE_MASK      (0x80000000)
386 #define SMU_CLOCK_GATING_CONTROL_RESERVED_MASK        (0x7FF0FFF0)
387 
388 #define SMU_CGUCR_GEN_VAL(name, value) \
389 	SCU_GEN_VALUE(SMU_CLOCK_GATING_CONTROL_##name, value)
390 
391 #define SMU_CGUCR_GEN_BIT(name) \
392 	SCU_GEN_BIT(SMU_CLOCK_GATING_CONTROL_##name)
393 
394 /* -------------------------------------------------------------------------- */
395 
396 #define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_SHIFT      (0)
397 #define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_MASK       (0x00000001)
398 #define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_SHIFT    (1)
399 #define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_MASK     (0x00000002)
400 #define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_SHIFT     (16)
401 #define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_MASK      (0x00010000)
402 #define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_SHIFT   (17)
403 #define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_MASK    (0x00020000)
404 #define SMU_CONTROL_STATUS_RESERVED_MASK                        (0xFFFCFFFC)
405 
406 #define SMU_SMUCSR_GEN_BIT(name) \
407 	SCU_GEN_BIT(SMU_CONTROL_STATUS_ ## name)
408 
409 #define SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED	\
410 	(SMU_SMUCSR_GEN_BIT(SCHEDULER_RAM_INIT_COMPLETED))
411 
412 #define SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED	\
413 	(SMU_SMUCSR_GEN_BIT(CONTEXT_RAM_INIT_COMPLETED))
414 
415 #define SCU_RAM_INIT_COMPLETED \
416 	(\
417 		SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED \
418 		| SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED \
419 	)
420 
421 /* -------------------------------------------------------------------------- */
422 
423 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_SHIFT  (0)
424 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_MASK   (0x00000001)
425 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_SHIFT  (1)
426 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_MASK   (0x00000002)
427 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_SHIFT  (2)
428 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_MASK   (0x00000004)
429 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_SHIFT  (3)
430 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_MASK   (0x00000008)
431 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_SHIFT  (8)
432 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_MASK   (0x00000100)
433 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_SHIFT  (9)
434 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_MASK   (0x00000200)
435 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_SHIFT  (10)
436 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_MASK   (0x00000400)
437 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_SHIFT  (11)
438 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_MASK   (0x00000800)
439 
440 #define SMU_RESET_PROTOCOL_ENGINE(peg, pe) \
441 	((1 << (pe)) << ((peg) * 8))
442 
443 #define SMU_RESET_PEG_PROTOCOL_ENGINES(peg) \
444 	(\
445 		SMU_RESET_PROTOCOL_ENGINE(peg, 0) \
446 		| SMU_RESET_PROTOCOL_ENGINE(peg, 1) \
447 		| SMU_RESET_PROTOCOL_ENGINE(peg, 2) \
448 		| SMU_RESET_PROTOCOL_ENGINE(peg, 3) \
449 	)
450 
451 #define SMU_RESET_ALL_PROTOCOL_ENGINES() \
452 	(\
453 		SMU_RESET_PEG_PROTOCOL_ENGINES(0) \
454 		| SMU_RESET_PEG_PROTOCOL_ENGINES(1) \
455 	)
456 
457 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_SHIFT  (16)
458 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_MASK   (0x00010000)
459 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_SHIFT  (17)
460 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_MASK   (0x00020000)
461 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_SHIFT  (18)
462 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_MASK   (0x00040000)
463 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_SHIFT  (19)
464 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_MASK   (0x00080000)
465 
466 #define SMU_RESET_WIDE_PORT_QUEUE(peg, wide_port) \
467 	((1 << ((wide_port) / 2)) << ((peg) * 2) << 16)
468 
469 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_SHIFT      (20)
470 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_MASK       (0x00100000)
471 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_SHIFT      (21)
472 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_MASK       (0x00200000)
473 #define SMU_SOFTRESET_CONTROL_RESET_SCU_SHIFT       (22)
474 #define SMU_SOFTRESET_CONTROL_RESET_SCU_MASK        (0x00400000)
475 
476 /*
477  * It seems to make sense that if you are going to reset the protocol
478  * engine group that you would also reset all of the protocol engines */
479 #define SMU_RESET_PROTOCOL_ENGINE_GROUP(peg) \
480 	(\
481 		(1 << ((peg) + 20)) \
482 		| SMU_RESET_WIDE_PORT_QUEUE(peg, 0) \
483 		| SMU_RESET_WIDE_PORT_QUEUE(peg, 1) \
484 		| SMU_RESET_PEG_PROTOCOL_ENGINES(peg) \
485 	)
486 
487 #define SMU_RESET_ALL_PROTOCOL_ENGINE_GROUPS() \
488 	(\
489 		SMU_RESET_PROTOCOL_ENGINE_GROUP(0) \
490 		| SMU_RESET_PROTOCOL_ENGINE_GROUP(1) \
491 	)
492 
493 #define SMU_RESET_SCU()  (0xFFFFFFFF)
494 
495 
496 
497 /* ***************************************************************************** */
498 #define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_SHIFT              (0)
499 #define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_MASK               (0x00000FFF)
500 #define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_SHIFT                (16)
501 #define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_MASK                 (0x0FFF0000)
502 #define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_SHIFT    (31)
503 #define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_MASK     (0x80000000)
504 #define SMU_TASK_CONTEXT_ASSIGNMENT_RESERVED_MASK               (0x7000F000)
505 
506 #define SMU_TCA_GEN_VAL(name, value) \
507 	SCU_GEN_VALUE(SMU_TASK_CONTEXT_ASSIGNMENT_ ## name, value)
508 
509 #define SMU_TCA_GEN_BIT(name) \
510 	SCU_GEN_BIT(SMU_TASK_CONTEXT_ASSIGNMENT_ ## name)
511 
512 /* ***************************************************************************** */
513 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_SHIFT   (0)
514 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_MASK    (0x00000FFF)
515 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_RESERVED_MASK      (0xFFFFF000)
516 
517 #define SCU_UFQC_GEN_VAL(name, value) \
518 	SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_ ## name, value)
519 
520 #define SCU_UFQC_QUEUE_SIZE_SET(value) \
521 	SCU_UFQC_GEN_VAL(QUEUE_SIZE, value)
522 
523 /* ***************************************************************************** */
524 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_SHIFT      (0)
525 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_MASK       (0x00000FFF)
526 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_SHIFT    (12)
527 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_MASK     (0x00001000)
528 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_RESERVED_MASK      (0xFFFFE000)
529 
530 #define SCU_UFQPP_GEN_VAL(name, value) \
531 	SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_ ## name, value)
532 
533 #define SCU_UFQPP_GEN_BIT(name)	\
534 	SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_ ## name)
535 
536 /*
537  * *****************************************************************************
538  * * SDMA Registers
539  * ***************************************************************************** */
540 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_SHIFT      (0)
541 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_MASK       (0x00000FFF)
542 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_SHIFT    (12)
543 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_MASK     (12)
544 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_SHIFT   (31)
545 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_MASK    (0x80000000)
546 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_RESERVED_MASK      (0x7FFFE000)
547 
548 #define SCU_UFQGP_GEN_VAL(name, value) \
549 	SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ ## name, value)
550 
551 #define SCU_UFQGP_GEN_BIT(name)	\
552 	SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ ## name)
553 
554 #define SCU_UFQGP_CYCLE_BIT(value) \
555 	SCU_UFQGP_GEN_BIT(CYCLE_BIT, value)
556 
557 #define SCU_UFQGP_GET_POINTER(value) \
558 	SCU_UFQGP_GEN_VALUE(POINTER, value)
559 
560 #define SCU_UFQGP_ENABLE(value)	\
561 	(SCU_UFQGP_GEN_BIT(ENABLE) | value)
562 
563 #define SCU_UFQGP_DISABLE(value) \
564 	(~SCU_UFQGP_GEN_BIT(ENABLE) & value)
565 
566 #define SCU_UFQGP_VALUE(bit, value) \
567 	(SCU_UFQGP_CYCLE_BIT(bit) | SCU_UFQGP_GET_POINTER(value))
568 
569 /* ***************************************************************************** */
570 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SHIFT                               (0)
571 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_MASK                                (0x0000FFFF)
572 #define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT                    (16)
573 #define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK                     (0x00010000)
574 #define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_SHIFT                            (17)
575 #define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_MASK                             (0x00020000)
576 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_SHIFT                   (18)
577 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_MASK                    (0x00040000)
578 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_SHIFT               (19)
579 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_MASK                (0x00080000)
580 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_SHIFT     (20)
581 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_MASK      (0x00100000)
582 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_SHIFT        (21)
583 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_MASK         (0x00200000)
584 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_SHIFT                        (22)
585 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_MASK                         (0x00400000)
586 #define SCU_PDMA_CONFIGURATION_RESERVED_MASK                                        (0xFF800000)
587 
588 #define SCU_PDMACR_GEN_VALUE(name, value) \
589 	SCU_GEN_VALUE(SCU_PDMA_CONFIGURATION_ ## name, value)
590 
591 #define SCU_PDMACR_GEN_BIT(name) \
592 	SCU_GEN_BIT(SCU_PDMA_CONFIGURATION_ ## name)
593 
594 #define SCU_PDMACR_BE_GEN_BIT(name) \
595 	SCU_PCMACR_GEN_BIT(BIG_ENDIAN_CONTROL_ ## name)
596 
597 /* ***************************************************************************** */
598 #define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT                    (8)
599 #define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK                     (0x00000100)
600 
601 #define SCU_CDMACR_GEN_BIT(name) \
602 	SCU_GEN_BIT(SCU_CDMA_CONFIGURATION_ ## name)
603 
604 /*
605  * *****************************************************************************
606  * * SCU Link Layer Registers
607  * ***************************************************************************** */
608 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_SHIFT             (0)
609 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_MASK              (0x000000FF)
610 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_SHIFT           (8)
611 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_MASK            (0x0000FF00)
612 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_SHIFT   (16)
613 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_MASK    (0x00FF0000)
614 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_SHIFT  (24)
615 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_MASK   (0xFF000000)
616 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_REQUIRED_MASK             (0x00000000)
617 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_DEFAULT_MASK              (0x7D00676F)
618 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_RESERVED_MASK             (0x00FF0000)
619 
620 #define SCU_SAS_SPDTOV_GEN_VALUE(name, value) \
621 	SCU_GEN_VALUE(SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_ ## name, value)
622 
623 
624 #define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_SHIFT            (2)
625 #define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_MASK             (0x00000004)
626 #define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_SHIFT  (4)
627 #define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_MASK   (0x00000010)
628 #define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_SHIFT     (5)
629 #define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_MASK      (0x00000020)
630 #define SCU_LINK_STATUS_RESERVED_MASK                       (0xFFFFFFCD)
631 
632 #define SCU_SAS_LLSTA_GEN_BIT(name) \
633 	SCU_GEN_BIT(SCU_LINK_STATUS_ ## name)
634 
635 
636 /* TODO: Where is the SATA_PSELTOV register? */
637 
638 /*
639  * *****************************************************************************
640  * * SCU SAS Maximum Arbitration Wait Time Timeout Register
641  * ***************************************************************************** */
642 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_SHIFT       (0)
643 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_MASK        (0x00007FFF)
644 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_SHIFT       (15)
645 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_MASK        (0x00008000)
646 
647 #define SCU_SAS_MAWTTOV_GEN_VALUE(name, value) \
648 	SCU_GEN_VALUE(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_ ## name, value)
649 
650 #define SCU_SAS_MAWTTOV_GEN_BIT(name) \
651 	SCU_GEN_BIT(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_ ## name)
652 
653 
654 /*
655  * TODO: Where is the SAS_LNKTOV regsiter?
656  * TODO: Where is the SAS_PHYTOV register? */
657 
658 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_SHIFT            (1)
659 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_MASK             (0x00000002)
660 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_SHIFT            (2)
661 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_MASK             (0x00000004)
662 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_SHIFT            (3)
663 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_MASK             (0x00000008)
664 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_SHIFT          (8)
665 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_MASK           (0x00000100)
666 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_SHIFT         (9)
667 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_MASK          (0x00000200)
668 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_SHIFT         (10)
669 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_MASK          (0x00000400)
670 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_SHIFT         (11)
671 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_MASK          (0x00000800)
672 #define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_SHIFT           (16)
673 #define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_MASK            (0x000F0000)
674 #define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_SHIFT    (24)
675 #define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_MASK     (0x0F000000)
676 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_SHIFT           (28)
677 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_MASK            (0x70000000)
678 #define SCU_SAS_TRANSMIT_IDENTIFICATION_RESERVED_MASK               (0x80F0F1F1)
679 
680 #define SCU_SAS_TIID_GEN_VAL(name, value) \
681 	SCU_GEN_VALUE(SCU_SAS_TRANSMIT_IDENTIFICATION_ ## name, value)
682 
683 #define SCU_SAS_TIID_GEN_BIT(name) \
684 	SCU_GEN_BIT(SCU_SAS_TRANSMIT_IDENTIFICATION_ ## name)
685 
686 /* SAS Identify Frame PHY Identifier Register */
687 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_SHIFT      (16)
688 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_MASK       (0x00010000)
689 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_SHIFT   (17)
690 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_MASK    (0x00020000)
691 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_SHIFT  (18)
692 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_MASK   (0x00040000)
693 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_SHIFT                       (24)
694 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_MASK                        (0xFF000000)
695 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_RESERVED_MASK                  (0x00F800FF)
696 
697 #define SCU_SAS_TIPID_GEN_VALUE(name, value) \
698 	SCU_GEN_VALUE(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ ## name, value)
699 
700 #define SCU_SAS_TIPID_GEN_BIT(name) \
701 	SCU_GEN_BIT(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ ## name)
702 
703 
704 #define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_SHIFT                     (4)
705 #define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_MASK                      (0x00000010)
706 #define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_SHIFT                          (6)
707 #define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_MASK                           (0x00000040)
708 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_SHIFT                   (7)
709 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_MASK                    (0x00000080)
710 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_SHIFT                 (8)
711 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_MASK                  (0x00000100)
712 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_SHIFT            (9)
713 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_MASK             (0x00000200)
714 #define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_SHIFT             (11)
715 #define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_MASK              (0x00000800)
716 #define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_SHIFT                    (12)
717 #define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_MASK                     (0x00001000)
718 #define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_SHIFT      (13)
719 #define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_MASK       (0x00002000)
720 #define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_SHIFT                          (14)
721 #define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_MASK                           (0x00004000)
722 #define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_SHIFT                          (15)
723 #define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_MASK                           (0x00008000)
724 #define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_SHIFT        (23)
725 #define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_MASK         (0x00800000)
726 #define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_SHIFT              (27)
727 #define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_MASK               (0x08000000)
728 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_SHIFT    (28)
729 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_MASK     (0x10000000)
730 #define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_SHIFT                           (29)
731 #define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_MASK                            (0x20000000)
732 #define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_SHIFT                    (30)
733 #define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_MASK                     (0x40000000)
734 #define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_SHIFT                   (31)
735 #define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_MASK                    (0x80000000)
736 #define SCU_SAS_PHY_CONFIGURATION_REQUIRED_MASK                             (0x0100000F)
737 #define SCU_SAS_PHY_CONFIGURATION_DEFAULT_MASK                              (0x4180100F)
738 #define SCU_SAS_PHY_CONFIGURATION_RESERVED_MASK                             (0x00000000)
739 
740 #define SCU_SAS_PCFG_GEN_BIT(name) \
741 	SCU_GEN_BIT(SCU_SAS_PHY_CONFIGURATION_ ## name)
742 
743 #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_SHIFT      (0)
744 #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_MASK       (0x000007FF)
745 #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_SHIFT    (16)
746 #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_MASK     (0x00ff0000)
747 
748 #define SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(name, value) \
749 	SCU_GEN_VALUE(SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_##name, value)
750 
751 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_SHIFT    (0)
752 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_MASK     (0x0003FFFF)
753 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_SHIFT   (31)
754 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_MASK    (0x80000000)
755 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_RESERVED_MASK  (0x7FFC0000)
756 
757 #define SCU_ENSPINUP_GEN_VAL(name, value) \
758 	SCU_GEN_VALUE(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ ## name, value)
759 
760 #define SCU_ENSPINUP_GEN_BIT(name) \
761 	SCU_GEN_BIT(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ ## name)
762 
763 
764 #define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_SHIFT     (1)
765 #define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_MASK      (0x00000002)
766 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_SHIFT       (4)
767 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_MASK        (0x000000F0)
768 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_SHIFT     (8)
769 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_MASK      (0x00000100)
770 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_SHIFT      (9)
771 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_MASK       (0x00000201)
772 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_SHIFT     (10)
773 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_MASK      (0x00000401)
774 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_SHIFT      (11)
775 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_MASK       (0x00000801)
776 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_SHIFT     (12)
777 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_MASK      (0x00001001)
778 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_SHIFT      (13)
779 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_MASK       (0x00002001)
780 #define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_SHIFT   (31)
781 #define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_MASK    (0x80000000)
782 #define SCU_LINK_LAYER_PHY_CAPABILITIES_DEFAULT_MASK        (0x00003F01)
783 #define SCU_LINK_LAYER_PHY_CAPABILITIES_REQUIRED_MASK       (0x00000001)
784 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RESERVED_MASK       (0x7FFFC00D)
785 
786 #define SCU_SAS_PHYCAP_GEN_VAL(name, value) \
787 	SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_CAPABILITIES_ ## name, value)
788 
789 #define SCU_SAS_PHYCAP_GEN_BIT(name) \
790 	SCU_GEN_BIT(SCU_LINK_LAYER_PHY_CAPABILITIES_ ## name)
791 
792 
793 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_SHIFT  (0)
794 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_MASK   (0x000000FF)
795 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_SHIFT         (31)
796 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_MASK          (0x80000000)
797 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_RESERVED_MASK                          (0x7FFFFF00)
798 
799 #define SCU_PSZGCR_GEN_VAL(name, value)	\
800 	SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_ ## name, value)
801 
802 #define SCU_PSZGCR_GEN_BIT(name) \
803 	SCU_GEN_BIT(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_ ## name)
804 
805 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_SHIFT        (1)
806 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_MASK         (0x00000002)
807 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_SHIFT      (2)
808 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_MASK       (0x00000004)
809 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_SHIFT        (4)
810 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_MASK         (0x00000010)
811 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_SHIFT      (5)
812 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_MASK       (0x00000020)
813 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_SHIFT (16)
814 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_MASK  (0x00030000)
815 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_SHIFT      (19)
816 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_MASK       (0x00080000)
817 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_SHIFT (20)
818 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_MASK  (0x00300000)
819 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_SHIFT      (23)
820 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_MASK       (0x00800000)
821 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_SHIFT (24)
822 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_MASK  (0x03000000)
823 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_SHIFT      (27)
824 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_MASK       (0x08000000)
825 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_SHIFT (28)
826 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_MASK  (0x30000000)
827 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_SHIFT      (31)
828 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_MASK       (0x80000000)
829 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_RESERVED_MASK             (0x4444FFC9)
830 
831 #define SCU_PEG_SCUVZECR_GEN_VAL(name, val) \
832 	SCU_GEN_VALUE(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ ## name, val)
833 
834 #define SCU_PEG_SCUVZECR_GEN_BIT(name) \
835 	SCU_GEN_BIT(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ ## name)
836 
837 
838 /*
839  * *****************************************************************************
840  * * Port Task Scheduler registers shift and mask values
841  * ***************************************************************************** */
842 #define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_SHIFT     (0)
843 #define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_MASK      (0x0000FFFF)
844 #define SCU_PTSG_CONTROL_TASK_TIMEOUT_SHIFT         (16)
845 #define SCU_PTSG_CONTROL_TASK_TIMEOUT_MASK          (0x00FF0000)
846 #define SCU_PTSG_CONTROL_PTSG_ENABLE_SHIFT          (24)
847 #define SCU_PTSG_CONTROL_PTSG_ENABLE_MASK           (0x01000000)
848 #define SCU_PTSG_CONTROL_ETM_ENABLE_SHIFT           (25)
849 #define SCU_PTSG_CONTROL_ETM_ENABLE_MASK            (0x02000000)
850 #define SCU_PTSG_CONTROL_DEFAULT_MASK               (0x00020002)
851 #define SCU_PTSG_CONTROL_REQUIRED_MASK              (0x00000000)
852 #define SCU_PTSG_CONTROL_RESERVED_MASK              (0xFC000000)
853 
854 #define SCU_PTSGCR_GEN_VAL(name, val) \
855 	SCU_GEN_VALUE(SCU_PTSG_CONTROL_ ## name, val)
856 
857 #define SCU_PTSGCR_GEN_BIT(name) \
858 	SCU_GEN_BIT(SCU_PTSG_CONTROL_ ## name)
859 
860 
861 /* ***************************************************************************** */
862 #define SCU_PTSG_REAL_TIME_CLOCK_SHIFT          (0)
863 #define SCU_PTSG_REAL_TIME_CLOCK_MASK           (0x0000FFFF)
864 #define SCU_PTSG_REAL_TIME_CLOCK_RESERVED_MASK  (0xFFFF0000)
865 
866 #define SCU_RTCR_GEN_VAL(name, val) \
867 	SCU_GEN_VALUE(SCU_PTSG_ ## name, val)
868 
869 
870 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_SHIFT  (0)
871 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_MASK   (0x00FFFFFF)
872 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_RESERVED_MASK          (0xFF000000)
873 
874 #define SCU_RTCCR_GEN_VAL(name, val) \
875 	SCU_GEN_VALUE(SCU_PTSG_REAL_TIME_CLOCK_CONTROL_ ## name, val)
876 
877 
878 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_SHIFT  (0)
879 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_MASK   (0x00000001)
880 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_SHIFT   (1)
881 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_MASK    (0x00000002)
882 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_RESERVED_MASK  (0xFFFFFFFC)
883 
884 #define SCU_PTSxCR_GEN_BIT(name) \
885 	SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ ## name)
886 
887 
888 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_SHIFT             (0)
889 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_MASK              (0x00000001)
890 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_SHIFT    (1)
891 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_MASK     (0x00000002)
892 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_SHIFT             (2)
893 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_MASK              (0x00000004)
894 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_RESERVED_MASK                   (0xFFFFFFF8)
895 
896 #define SCU_PTSxSR_GEN_BIT(name) \
897 	SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ ## name)
898 
899 /*
900  * *****************************************************************************
901  * * SMU Registers
902  * ***************************************************************************** */
903 
904 /*
905  * ----------------------------------------------------------------------------
906  * SMU Registers
907  * These registers are based off of BAR0
908  *
909  * To calculate the offset for other functions use
910  *       BAR0 + FN# * SystemPageSize * 2
911  *
912  * The TCA is only accessable from FN#0 (Physical Function) and each
913  * is programmed by (BAR0 + SCU_SMU_TCA_OFFSET + (FN# * 0x04)) or
914  *    TCA0 for FN#0 is at BAR0 + 0x0400
915  *    TCA1 for FN#1 is at BAR0 + 0x0404
916  *    etc.
917  * ----------------------------------------------------------------------------
918  * Accessable to all FN#s */
919 #define SCU_SMU_PCP_OFFSET          0x0000
920 #define SCU_SMU_AMR_OFFSET          0x0004
921 #define SCU_SMU_ISR_OFFSET          0x0010
922 #define SCU_SMU_IMR_OFFSET          0x0014
923 #define SCU_SMU_ICC_OFFSET          0x0018
924 #define SCU_SMU_HTTLBAR_OFFSET      0x0020
925 #define SCU_SMU_HTTUBAR_OFFSET      0x0024
926 #define SCU_SMU_TCR_OFFSET          0x0028
927 #define SCU_SMU_CQLBAR_OFFSET       0x0030
928 #define SCU_SMU_CQUBAR_OFFSET       0x0034
929 #define SCU_SMU_CQPR_OFFSET         0x0040
930 #define SCU_SMU_CQGR_OFFSET         0x0044
931 #define SCU_SMU_CQC_OFFSET          0x0048
932 /* Accessable to FN#0 only */
933 #define SCU_SMU_RNCLBAR_OFFSET      0x0080
934 #define SCU_SMU_RNCUBAR_OFFSET      0x0084
935 #define SCU_SMU_DCC_OFFSET          0x0090
936 #define SCU_SMU_DFC_OFFSET          0x0094
937 #define SCU_SMU_SMUCSR_OFFSET       0x0098
938 #define SCU_SMU_SCUSRCR_OFFSET      0x009C
939 #define SCU_SMU_SMAW_OFFSET         0x00A0
940 #define SCU_SMU_SMDW_OFFSET         0x00A4
941 /* Accessable to FN#0 only */
942 #define SCU_SMU_TCA_OFFSET          0x0400
943 /* Accessable to all FN#s */
944 #define SCU_SMU_MT_MLAR0_OFFSET     0x2000
945 #define SCU_SMU_MT_MUAR0_OFFSET     0x2004
946 #define SCU_SMU_MT_MDR0_OFFSET      0x2008
947 #define SCU_SMU_MT_VCR0_OFFSET      0x200C
948 #define SCU_SMU_MT_MLAR1_OFFSET     0x2010
949 #define SCU_SMU_MT_MUAR1_OFFSET     0x2014
950 #define SCU_SMU_MT_MDR1_OFFSET      0x2018
951 #define SCU_SMU_MT_VCR1_OFFSET      0x201C
952 #define SCU_SMU_MPBA_OFFSET         0x3000
953 
954 /**
955  * struct smu_registers - These are the SMU registers
956  *
957  *
958  */
959 struct smu_registers {
960 /* 0x0000 PCP */
961 	u32 post_context_port;
962 /* 0x0004 AMR */
963 	u32 address_modifier;
964 	u32 reserved_08;
965 	u32 reserved_0C;
966 /* 0x0010 ISR */
967 	u32 interrupt_status;
968 /* 0x0014 IMR */
969 	u32 interrupt_mask;
970 /* 0x0018 ICC */
971 	u32 interrupt_coalesce_control;
972 	u32 reserved_1C;
973 /* 0x0020 HTTLBAR */
974 	u32 host_task_table_lower;
975 /* 0x0024 HTTUBAR */
976 	u32 host_task_table_upper;
977 /* 0x0028 TCR */
978 	u32 task_context_range;
979 	u32 reserved_2C;
980 /* 0x0030 CQLBAR */
981 	u32 completion_queue_lower;
982 /* 0x0034 CQUBAR */
983 	u32 completion_queue_upper;
984 	u32 reserved_38;
985 	u32 reserved_3C;
986 /* 0x0040 CQPR */
987 	u32 completion_queue_put;
988 /* 0x0044 CQGR */
989 	u32 completion_queue_get;
990 /* 0x0048 CQC */
991 	u32 completion_queue_control;
992 	u32 reserved_4C;
993 	u32 reserved_5x[4];
994 	u32 reserved_6x[4];
995 	u32 reserved_7x[4];
996 /*
997  * Accessable to FN#0 only
998  * 0x0080 RNCLBAR */
999 	u32 remote_node_context_lower;
1000 /* 0x0084 RNCUBAR */
1001 	u32 remote_node_context_upper;
1002 	u32 reserved_88;
1003 	u32 reserved_8C;
1004 /* 0x0090 DCC */
1005 	u32 device_context_capacity;
1006 /* 0x0094 DFC */
1007 	u32 device_function_capacity;
1008 /* 0x0098 SMUCSR */
1009 	u32 control_status;
1010 /* 0x009C SCUSRCR */
1011 	u32 soft_reset_control;
1012 /* 0x00A0 SMAW */
1013 	u32 mmr_address_window;
1014 /* 0x00A4 SMDW */
1015 	u32 mmr_data_window;
1016 /* 0x00A8 CGUCR */
1017 	u32 clock_gating_control;
1018 /* 0x00AC CGUPC */
1019 	u32 clock_gating_performance;
1020 /* A whole bunch of reserved space */
1021 	u32 reserved_Bx[4];
1022 	u32 reserved_Cx[4];
1023 	u32 reserved_Dx[4];
1024 	u32 reserved_Ex[4];
1025 	u32 reserved_Fx[4];
1026 	u32 reserved_1xx[64];
1027 	u32 reserved_2xx[64];
1028 	u32 reserved_3xx[64];
1029 /*
1030  * Accessable to FN#0 only
1031  * 0x0400 TCA */
1032 	u32 task_context_assignment[256];
1033 /* MSI-X registers not included */
1034 };
1035 
1036 /*
1037  * *****************************************************************************
1038  * SDMA Registers
1039  * ***************************************************************************** */
1040 #define SCU_SDMA_BASE               0x6000
1041 #define SCU_SDMA_PUFATLHAR_OFFSET   0x0000
1042 #define SCU_SDMA_PUFATUHAR_OFFSET   0x0004
1043 #define SCU_SDMA_UFLHBAR_OFFSET     0x0008
1044 #define SCU_SDMA_UFUHBAR_OFFSET     0x000C
1045 #define SCU_SDMA_UFQC_OFFSET        0x0010
1046 #define SCU_SDMA_UFQPP_OFFSET       0x0014
1047 #define SCU_SDMA_UFQGP_OFFSET       0x0018
1048 #define SCU_SDMA_PDMACR_OFFSET      0x001C
1049 #define SCU_SDMA_CDMACR_OFFSET      0x0080
1050 
1051 /**
1052  * struct scu_sdma_registers - These are the SCU SDMA Registers
1053  *
1054  *
1055  */
1056 struct scu_sdma_registers {
1057 /* 0x0000 PUFATLHAR */
1058 	u32 uf_address_table_lower;
1059 /* 0x0004 PUFATUHAR */
1060 	u32 uf_address_table_upper;
1061 /* 0x0008 UFLHBAR */
1062 	u32 uf_header_base_address_lower;
1063 /* 0x000C UFUHBAR */
1064 	u32 uf_header_base_address_upper;
1065 /* 0x0010 UFQC */
1066 	u32 unsolicited_frame_queue_control;
1067 /* 0x0014 UFQPP */
1068 	u32 unsolicited_frame_put_pointer;
1069 /* 0x0018 UFQGP */
1070 	u32 unsolicited_frame_get_pointer;
1071 /* 0x001C PDMACR */
1072 	u32 pdma_configuration;
1073 /* Reserved until offset 0x80 */
1074 	u32 reserved_0020_007C[0x18];
1075 /* 0x0080 CDMACR */
1076 	u32 cdma_configuration;
1077 /* Remainder SDMA register space */
1078 	u32 reserved_0084_0400[0xDF];
1079 
1080 };
1081 
1082 /*
1083  * *****************************************************************************
1084  * * SCU Link Registers
1085  * ***************************************************************************** */
1086 #define SCU_PEG0_OFFSET    0x0000
1087 #define SCU_PEG1_OFFSET    0x8000
1088 
1089 #define SCU_TL0_OFFSET     0x0000
1090 #define SCU_TL1_OFFSET     0x0400
1091 #define SCU_TL2_OFFSET     0x0800
1092 #define SCU_TL3_OFFSET     0x0C00
1093 
1094 #define SCU_LL_OFFSET      0x0080
1095 #define SCU_LL0_OFFSET     (SCU_TL0_OFFSET + SCU_LL_OFFSET)
1096 #define SCU_LL1_OFFSET     (SCU_TL1_OFFSET + SCU_LL_OFFSET)
1097 #define SCU_LL2_OFFSET     (SCU_TL2_OFFSET + SCU_LL_OFFSET)
1098 #define SCU_LL3_OFFSET     (SCU_TL3_OFFSET + SCU_LL_OFFSET)
1099 
1100 /* Transport Layer Offsets (PEG + TL) */
1101 #define SCU_TLCR_OFFSET         0x0000
1102 #define SCU_TLADTR_OFFSET       0x0004
1103 #define SCU_TLTTMR_OFFSET       0x0008
1104 #define SCU_TLEECR0_OFFSET      0x000C
1105 #define SCU_STPTLDARNI_OFFSET   0x0010
1106 
1107 
1108 #define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_SHIFT    (0)
1109 #define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_MASK     (0x00000001)
1110 #define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_SHIFT (1)
1111 #define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_MASK  (0x00000002)
1112 #define SCU_TLCR_STP_WRITE_DATA_PREFETCH_SHIFT     (3)
1113 #define SCU_TLCR_STP_WRITE_DATA_PREFETCH_MASK      (0x00000008)
1114 #define SCU_TLCR_CMD_NAK_STATUS_CODE_SHIFT         (4)
1115 #define SCU_TLCR_CMD_NAK_STATUS_CODE_MASK          (0x00000010)
1116 #define SCU_TLCR_RESERVED_MASK                     (0xFFFFFFEB)
1117 
1118 #define SCU_TLCR_GEN_BIT(name) \
1119 	SCU_GEN_BIT(SCU_TLCR_ ## name)
1120 
1121 /**
1122  * struct scu_transport_layer_registers - These are the SCU Transport Layer
1123  *    registers
1124  *
1125  *
1126  */
1127 struct scu_transport_layer_registers {
1128 	/* 0x0000 TLCR */
1129 	u32 control;
1130 	/* 0x0004 TLADTR */
1131 	u32 arbitration_delay_timer;
1132 	/* 0x0008 TLTTMR */
1133 	u32 timer_test_mode;
1134 	/* 0x000C reserved */
1135 	u32 reserved_0C;
1136 	/* 0x0010 STPTLDARNI */
1137 	u32 stp_rni;
1138 	/* 0x0014 TLFEWPORCTRL */
1139 	u32 tlfe_wpo_read_control;
1140 	/* 0x0018 TLFEWPORDATA */
1141 	u32 tlfe_wpo_read_data;
1142 	/* 0x001C RXTLSSCSR1 */
1143 	u32 rxtl_single_step_control_status_1;
1144 	/* 0x0020 RXTLSSCSR2 */
1145 	u32 rxtl_single_step_control_status_2;
1146 	/* 0x0024 AWTRDDCR */
1147 	u32 tlfe_awt_retry_delay_debug_control;
1148 	/* Remainder of TL memory space */
1149 	u32 reserved_0028_007F[0x16];
1150 
1151 };
1152 
1153 /* Protocol Engine Group Registers */
1154 #define SCU_SCUVZECRx_OFFSET        0x1080
1155 
1156 /* Link Layer Offsets (PEG + TL + LL) */
1157 #define SCU_SAS_SPDTOV_OFFSET       0x0000
1158 #define SCU_SAS_LLSTA_OFFSET        0x0004
1159 #define SCU_SATA_PSELTOV_OFFSET     0x0008
1160 #define SCU_SAS_TIMETOV_OFFSET      0x0010
1161 #define SCU_SAS_LOSTOT_OFFSET       0x0014
1162 #define SCU_SAS_LNKTOV_OFFSET       0x0018
1163 #define SCU_SAS_PHYTOV_OFFSET       0x001C
1164 #define SCU_SAS_AFERCNT_OFFSET      0x0020
1165 #define SCU_SAS_WERCNT_OFFSET       0x0024
1166 #define SCU_SAS_TIID_OFFSET         0x0028
1167 #define SCU_SAS_TIDNH_OFFSET        0x002C
1168 #define SCU_SAS_TIDNL_OFFSET        0x0030
1169 #define SCU_SAS_TISSAH_OFFSET       0x0034
1170 #define SCU_SAS_TISSAL_OFFSET       0x0038
1171 #define SCU_SAS_TIPID_OFFSET        0x003C
1172 #define SCU_SAS_TIRES2_OFFSET       0x0040
1173 #define SCU_SAS_ADRSTA_OFFSET       0x0044
1174 #define SCU_SAS_MAWTTOV_OFFSET      0x0048
1175 #define SCU_SAS_FRPLDFIL_OFFSET     0x0054
1176 #define SCU_SAS_RFCNT_OFFSET        0x0060
1177 #define SCU_SAS_TFCNT_OFFSET        0x0064
1178 #define SCU_SAS_RFDCNT_OFFSET       0x0068
1179 #define SCU_SAS_TFDCNT_OFFSET       0x006C
1180 #define SCU_SAS_LERCNT_OFFSET       0x0070
1181 #define SCU_SAS_RDISERRCNT_OFFSET   0x0074
1182 #define SCU_SAS_CRERCNT_OFFSET      0x0078
1183 #define SCU_STPCTL_OFFSET           0x007C
1184 #define SCU_SAS_PCFG_OFFSET         0x0080
1185 #define SCU_SAS_CLKSM_OFFSET        0x0084
1186 #define SCU_SAS_TXCOMWAKE_OFFSET    0x0088
1187 #define SCU_SAS_TXCOMINIT_OFFSET    0x008C
1188 #define SCU_SAS_TXCOMSAS_OFFSET     0x0090
1189 #define SCU_SAS_COMINIT_OFFSET      0x0094
1190 #define SCU_SAS_COMWAKE_OFFSET      0x0098
1191 #define SCU_SAS_COMSAS_OFFSET       0x009C
1192 #define SCU_SAS_SFERCNT_OFFSET      0x00A0
1193 #define SCU_SAS_CDFERCNT_OFFSET     0x00A4
1194 #define SCU_SAS_DNFERCNT_OFFSET     0x00A8
1195 #define SCU_SAS_PRSTERCNT_OFFSET    0x00AC
1196 #define SCU_SAS_CNTCTL_OFFSET       0x00B0
1197 #define SCU_SAS_SSPTOV_OFFSET       0x00B4
1198 #define SCU_FTCTL_OFFSET            0x00B8
1199 #define SCU_FRCTL_OFFSET            0x00BC
1200 #define SCU_FTWMRK_OFFSET           0x00C0
1201 #define SCU_ENSPINUP_OFFSET         0x00C4
1202 #define SCU_SAS_TRNTOV_OFFSET       0x00C8
1203 #define SCU_SAS_PHYCAP_OFFSET       0x00CC
1204 #define SCU_SAS_PHYCTL_OFFSET       0x00D0
1205 #define SCU_SAS_LLCTL_OFFSET        0x00D8
1206 #define SCU_AFE_XCVRCR_OFFSET       0x00DC
1207 #define SCU_AFE_LUTCR_OFFSET        0x00E0
1208 
1209 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_SHIFT          (0UL)
1210 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_MASK           (0x000000FFUL)
1211 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_SHIFT                 (8UL)
1212 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_MASK                  (0x0000FF00UL)
1213 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_SHIFT         (16UL)
1214 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_MASK          (0x00FF0000UL)
1215 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_SHIFT              (24UL)
1216 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_MASK               (0xFF000000UL)
1217 
1218 #define SCU_SAS_PHYTOV_GEN_VAL(name, value) \
1219 	SCU_GEN_VALUE(SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_##name, value)
1220 
1221 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_SHIFT                  (0)
1222 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_MASK                   (0x00000003)
1223 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1                   (0)
1224 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2                   (1)
1225 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3                   (2)
1226 #define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_SHIFT            (2)
1227 #define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_MASK             (0x000003FC)
1228 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_SHIFT   (16)
1229 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_MASK    (0x00010000)
1230 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_SHIFT (17)
1231 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_MASK  (0x00020000)
1232 #define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_SHIFT       (24)
1233 #define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_MASK        (0xFF000000)
1234 #define SCU_SAS_LINK_LAYER_CONTROL_RESERVED                             (0x00FCFC00)
1235 
1236 #define SCU_SAS_LLCTL_GEN_VAL(name, value) \
1237 	SCU_GEN_VALUE(SCU_SAS_LINK_LAYER_CONTROL_ ## name, value)
1238 
1239 #define SCU_SAS_LLCTL_GEN_BIT(name) \
1240 	SCU_GEN_BIT(SCU_SAS_LINK_LAYER_CONTROL_ ## name)
1241 
1242 
1243 /* #define SCU_FRXHECR_DCNT_OFFSET      0x00B0 */
1244 #define SCU_PSZGCR_OFFSET           0x00E4
1245 #define SCU_SAS_RECPHYCAP_OFFSET    0x00E8
1246 /* #define SCU_TX_LUTSEL_OFFSET         0x00B8 */
1247 
1248 #define SCU_SAS_PTxC_OFFSET         0x00D4 /* Same offset as SAS_TCTSTM */
1249 
1250 /**
1251  * struct scu_link_layer_registers - SCU Link Layer Registers
1252  *
1253  *
1254  */
1255 struct scu_link_layer_registers {
1256 /* 0x0000 SAS_SPDTOV */
1257 	u32 speed_negotiation_timers;
1258 /* 0x0004 SAS_LLSTA */
1259 	u32 link_layer_status;
1260 /* 0x0008 SATA_PSELTOV */
1261 	u32 port_selector_timeout;
1262 	u32 reserved0C;
1263 /* 0x0010 SAS_TIMETOV */
1264 	u32 timeout_unit_value;
1265 /* 0x0014 SAS_RCDTOV */
1266 	u32 rcd_timeout;
1267 /* 0x0018 SAS_LNKTOV */
1268 	u32 link_timer_timeouts;
1269 /* 0x001C SAS_PHYTOV */
1270 	u32 sas_phy_timeouts;
1271 /* 0x0020 SAS_AFERCNT */
1272 	u32 received_address_frame_error_counter;
1273 /* 0x0024 SAS_WERCNT */
1274 	u32 invalid_dword_counter;
1275 /* 0x0028 SAS_TIID */
1276 	u32 transmit_identification;
1277 /* 0x002C SAS_TIDNH */
1278 	u32 sas_device_name_high;
1279 /* 0x0030 SAS_TIDNL */
1280 	u32 sas_device_name_low;
1281 /* 0x0034 SAS_TISSAH */
1282 	u32 source_sas_address_high;
1283 /* 0x0038 SAS_TISSAL */
1284 	u32 source_sas_address_low;
1285 /* 0x003C SAS_TIPID */
1286 	u32 identify_frame_phy_id;
1287 /* 0x0040 SAS_TIRES2 */
1288 	u32 identify_frame_reserved;
1289 /* 0x0044 SAS_ADRSTA */
1290 	u32 received_address_frame;
1291 /* 0x0048 SAS_MAWTTOV */
1292 	u32 maximum_arbitration_wait_timer_timeout;
1293 /* 0x004C SAS_PTxC */
1294 	u32 transmit_primitive;
1295 /* 0x0050 SAS_RORES */
1296 	u32 error_counter_event_notification_control;
1297 /* 0x0054 SAS_FRPLDFIL */
1298 	u32 frxq_payload_fill_threshold;
1299 /* 0x0058 SAS_LLHANG_TOT */
1300 	u32 link_layer_hang_detection_timeout;
1301 	u32 reserved_5C;
1302 /* 0x0060 SAS_RFCNT */
1303 	u32 received_frame_count;
1304 /* 0x0064 SAS_TFCNT */
1305 	u32 transmit_frame_count;
1306 /* 0x0068 SAS_RFDCNT */
1307 	u32 received_dword_count;
1308 /* 0x006C SAS_TFDCNT */
1309 	u32 transmit_dword_count;
1310 /* 0x0070 SAS_LERCNT */
1311 	u32 loss_of_sync_error_count;
1312 /* 0x0074 SAS_RDISERRCNT */
1313 	u32 running_disparity_error_count;
1314 /* 0x0078 SAS_CRERCNT */
1315 	u32 received_frame_crc_error_count;
1316 /* 0x007C STPCTL */
1317 	u32 stp_control;
1318 /* 0x0080 SAS_PCFG */
1319 	u32 phy_configuration;
1320 /* 0x0084 SAS_CLKSM */
1321 	u32 clock_skew_management;
1322 /* 0x0088 SAS_TXCOMWAKE */
1323 	u32 transmit_comwake_signal;
1324 /* 0x008C SAS_TXCOMINIT */
1325 	u32 transmit_cominit_signal;
1326 /* 0x0090 SAS_TXCOMSAS */
1327 	u32 transmit_comsas_signal;
1328 /* 0x0094 SAS_COMINIT */
1329 	u32 cominit_control;
1330 /* 0x0098 SAS_COMWAKE */
1331 	u32 comwake_control;
1332 /* 0x009C SAS_COMSAS */
1333 	u32 comsas_control;
1334 /* 0x00A0 SAS_SFERCNT */
1335 	u32 received_short_frame_count;
1336 /* 0x00A4 SAS_CDFERCNT */
1337 	u32 received_frame_without_credit_count;
1338 /* 0x00A8 SAS_DNFERCNT */
1339 	u32 received_frame_after_done_count;
1340 /* 0x00AC SAS_PRSTERCNT */
1341 	u32 phy_reset_problem_count;
1342 /* 0x00B0 SAS_CNTCTL */
1343 	u32 counter_control;
1344 /* 0x00B4 SAS_SSPTOV */
1345 	u32 ssp_timer_timeout_values;
1346 /* 0x00B8 FTCTL */
1347 	u32 ftx_control;
1348 /* 0x00BC FRCTL */
1349 	u32 frx_control;
1350 /* 0x00C0 FTWMRK */
1351 	u32 ftx_watermark;
1352 /* 0x00C4 ENSPINUP */
1353 	u32 notify_enable_spinup_control;
1354 /* 0x00C8 SAS_TRNTOV */
1355 	u32 sas_training_sequence_timer_values;
1356 /* 0x00CC SAS_PHYCAP */
1357 	u32 phy_capabilities;
1358 /* 0x00D0 SAS_PHYCTL */
1359 	u32 phy_control;
1360 	u32 reserved_d4;
1361 /* 0x00D8 LLCTL */
1362 	u32 link_layer_control;
1363 /* 0x00DC AFE_XCVRCR */
1364 	u32 afe_xcvr_control;
1365 /* 0x00E0 AFE_LUTCR */
1366 	u32 afe_lookup_table_control;
1367 /* 0x00E4 PSZGCR */
1368 	u32 phy_source_zone_group_control;
1369 /* 0x00E8 SAS_RECPHYCAP */
1370 	u32 receive_phycap;
1371 	u32 reserved_ec;
1372 /* 0x00F0 SNAFERXRSTCTL */
1373 	u32 speed_negotiation_afe_rx_reset_control;
1374 /* 0x00F4 SAS_SSIPMCTL */
1375 	u32 power_management_control;
1376 /* 0x00F8 SAS_PSPREQ_PRIM */
1377 	u32 sas_pm_partial_request_primitive;
1378 /* 0x00FC SAS_PSSREQ_PRIM */
1379 	u32 sas_pm_slumber_request_primitive;
1380 /* 0x0100 SAS_PPSACK_PRIM */
1381 	u32 sas_pm_ack_primitive_register;
1382 /* 0x0104 SAS_PSNAK_PRIM */
1383 	u32 sas_pm_nak_primitive_register;
1384 /* 0x0108 SAS_SSIPMTOV */
1385 	u32 sas_primitive_timeout;
1386 	u32 reserved_10c;
1387 /* 0x0110 - 0x011C PLAPRDCTRLxREG */
1388 	u32 pla_product_control[4];
1389 /* 0x0120 PLAPRDSUMREG */
1390 	u32 pla_product_sum;
1391 /* 0x0124 PLACONTROLREG */
1392 	u32 pla_control;
1393 /* Remainder of memory space 896 bytes */
1394 	u32 reserved_0128_037f[0x96];
1395 
1396 };
1397 
1398 /*
1399  * 0x00D4 // Same offset as SAS_TCTSTM SAS_PTxC
1400  *   u32   primitive_transmit_control; */
1401 
1402 /*
1403  * ----------------------------------------------------------------------------
1404  * SGPIO
1405  * ---------------------------------------------------------------------------- */
1406 #define SCU_SGPIO_OFFSET         0x1400
1407 
1408 /* #define SCU_SGPIO_OFFSET         0x6000   // later moves to 0x1400 see HSD 652625 */
1409 #define SCU_SGPIO_SGICR_OFFSET   0x0000
1410 #define SCU_SGPIO_SGPBR_OFFSET   0x0004
1411 #define SCU_SGPIO_SGSDLR_OFFSET  0x0008
1412 #define SCU_SGPIO_SGSDUR_OFFSET  0x000C
1413 #define SCU_SGPIO_SGSIDLR_OFFSET 0x0010
1414 #define SCU_SGPIO_SGSIDUR_OFFSET 0x0014
1415 #define SCU_SGPIO_SGVSCR_OFFSET  0x0018
1416 /* Address from 0x0820 to 0x083C */
1417 #define SCU_SGPIO_SGODSR_OFFSET  0x0020
1418 
1419 /**
1420  * struct scu_sgpio_registers - SCU SGPIO Registers
1421  *
1422  *
1423  */
1424 struct scu_sgpio_registers {
1425 /* 0x0000 SGPIO_SGICR */
1426 	u32 interface_control;
1427 /* 0x0004 SGPIO_SGPBR */
1428 	u32 blink_rate;
1429 /* 0x0008 SGPIO_SGSDLR */
1430 	u32 start_drive_lower;
1431 /* 0x000C SGPIO_SGSDUR */
1432 	u32 start_drive_upper;
1433 /* 0x0010 SGPIO_SGSIDLR */
1434 	u32 serial_input_lower;
1435 /* 0x0014 SGPIO_SGSIDUR */
1436 	u32 serial_input_upper;
1437 /* 0x0018 SGPIO_SGVSCR */
1438 	u32 vendor_specific_code;
1439 /* 0x001C Reserved */
1440 	u32 reserved_001c;
1441 /* 0x0020 SGPIO_SGODSR */
1442 	u32 output_data_select[8];
1443 /* Remainder of memory space 256 bytes */
1444 	u32 reserved_1444_14ff[0x30];
1445 
1446 };
1447 
1448 /*
1449  * *****************************************************************************
1450  * * Defines for VIIT entry offsets
1451  * * Access additional entries by SCU_VIIT_BASE + index * 0x10
1452  * ***************************************************************************** */
1453 #define     SCU_VIIT_BASE     0x1c00
1454 
1455 struct scu_viit_registers {
1456 	u32 registers[256];
1457 };
1458 
1459 /*
1460  * *****************************************************************************
1461  * * SCU PORT TASK SCHEDULER REGISTERS
1462  * ***************************************************************************** */
1463 
1464 #define SCU_PTSG_BASE               0x1000
1465 
1466 #define SCU_PTSG_PTSGCR_OFFSET      0x0000
1467 #define SCU_PTSG_RTCR_OFFSET        0x0004
1468 #define SCU_PTSG_RTCCR_OFFSET       0x0008
1469 #define SCU_PTSG_PTS0CR_OFFSET      0x0010
1470 #define SCU_PTSG_PTS0SR_OFFSET      0x0014
1471 #define SCU_PTSG_PTS1CR_OFFSET      0x0018
1472 #define SCU_PTSG_PTS1SR_OFFSET      0x001C
1473 #define SCU_PTSG_PTS2CR_OFFSET      0x0020
1474 #define SCU_PTSG_PTS2SR_OFFSET      0x0024
1475 #define SCU_PTSG_PTS3CR_OFFSET      0x0028
1476 #define SCU_PTSG_PTS3SR_OFFSET      0x002C
1477 #define SCU_PTSG_PCSPE0CR_OFFSET    0x0030
1478 #define SCU_PTSG_PCSPE1CR_OFFSET    0x0034
1479 #define SCU_PTSG_PCSPE2CR_OFFSET    0x0038
1480 #define SCU_PTSG_PCSPE3CR_OFFSET    0x003C
1481 #define SCU_PTSG_ETMTSCCR_OFFSET    0x0040
1482 #define SCU_PTSG_ETMRNSCCR_OFFSET   0x0044
1483 
1484 /**
1485  * struct scu_port_task_scheduler_registers - These are the control/stats pairs
1486  *    for each Port Task Scheduler.
1487  *
1488  *
1489  */
1490 struct scu_port_task_scheduler_registers {
1491 	u32 control;
1492 	u32 status;
1493 };
1494 
1495 /**
1496  * struct scu_port_task_scheduler_group_registers - These are the PORT Task
1497  *    Scheduler registers
1498  *
1499  *
1500  */
1501 struct scu_port_task_scheduler_group_registers {
1502 /* 0x0000 PTSGCR */
1503 	u32 control;
1504 /* 0x0004 RTCR */
1505 	u32 real_time_clock;
1506 /* 0x0008 RTCCR */
1507 	u32 real_time_clock_control;
1508 /* 0x000C */
1509 	u32 reserved_0C;
1510 /*
1511  * 0x0010 PTS0CR
1512  * 0x0014 PTS0SR
1513  * 0x0018 PTS1CR
1514  * 0x001C PTS1SR
1515  * 0x0020 PTS2CR
1516  * 0x0024 PTS2SR
1517  * 0x0028 PTS3CR
1518  * 0x002C PTS3SR */
1519 	struct scu_port_task_scheduler_registers port[4];
1520 /*
1521  * 0x0030 PCSPE0CR
1522  * 0x0034 PCSPE1CR
1523  * 0x0038 PCSPE2CR
1524  * 0x003C PCSPE3CR */
1525 	u32 protocol_engine[4];
1526 /* 0x0040 ETMTSCCR */
1527 	u32 tc_scanning_interval_control;
1528 /* 0x0044 ETMRNSCCR */
1529 	u32 rnc_scanning_interval_control;
1530 /* Remainder of memory space 128 bytes */
1531 	u32 reserved_1048_107f[0x0E];
1532 
1533 };
1534 
1535 #define SCU_PTSG_SCUVZECR_OFFSET        0x003C
1536 
1537 /*
1538  * *****************************************************************************
1539  * * AFE REGISTERS
1540  * ***************************************************************************** */
1541 #define SCU_AFE_MMR_BASE                  0xE000
1542 
1543 /*
1544  * AFE 0 is at offset 0x0800
1545  * AFE 1 is at offset 0x0900
1546  * AFE 2 is at offset 0x0a00
1547  * AFE 3 is at offset 0x0b00 */
1548 struct scu_afe_transceiver {
1549 	/* 0x0000 AFE_XCVR_CTRL0 */
1550 	u32 afe_xcvr_control0;
1551 	/* 0x0004 AFE_XCVR_CTRL1 */
1552 	u32 afe_xcvr_control1;
1553 	/* 0x0008 */
1554 	u32 reserved_0008;
1555 	/* 0x000c afe_dfx_rx_control0 */
1556 	u32 afe_dfx_rx_control0;
1557 	/* 0x0010 AFE_DFX_RX_CTRL1 */
1558 	u32 afe_dfx_rx_control1;
1559 	/* 0x0014 */
1560 	u32 reserved_0014;
1561 	/* 0x0018 AFE_DFX_RX_STS0 */
1562 	u32 afe_dfx_rx_status0;
1563 	/* 0x001c AFE_DFX_RX_STS1 */
1564 	u32 afe_dfx_rx_status1;
1565 	/* 0x0020 */
1566 	u32 reserved_0020;
1567 	/* 0x0024 AFE_TX_CTRL */
1568 	u32 afe_tx_control;
1569 	/* 0x0028 AFE_TX_AMP_CTRL0 */
1570 	u32 afe_tx_amp_control0;
1571 	/* 0x002c AFE_TX_AMP_CTRL1 */
1572 	u32 afe_tx_amp_control1;
1573 	/* 0x0030 AFE_TX_AMP_CTRL2 */
1574 	u32 afe_tx_amp_control2;
1575 	/* 0x0034 AFE_TX_AMP_CTRL3 */
1576 	u32 afe_tx_amp_control3;
1577 	/* 0x0038 afe_tx_ssc_control */
1578 	u32 afe_tx_ssc_control;
1579 	/* 0x003c */
1580 	u32 reserved_003c;
1581 	/* 0x0040 AFE_RX_SSC_CTRL0 */
1582 	u32 afe_rx_ssc_control0;
1583 	/* 0x0044 AFE_RX_SSC_CTRL1 */
1584 	u32 afe_rx_ssc_control1;
1585 	/* 0x0048 AFE_RX_SSC_CTRL2 */
1586 	u32 afe_rx_ssc_control2;
1587 	/* 0x004c AFE_RX_EQ_STS0 */
1588 	u32 afe_rx_eq_status0;
1589 	/* 0x0050 AFE_RX_EQ_STS1 */
1590 	u32 afe_rx_eq_status1;
1591 	/* 0x0054 AFE_RX_CDR_STS */
1592 	u32 afe_rx_cdr_status;
1593 	/* 0x0058 */
1594 	u32 reserved_0058;
1595 	/* 0x005c AFE_CHAN_CTRL */
1596 	u32 afe_channel_control;
1597 	/* 0x0060-0x006c */
1598 	u32 reserved_0060_006c[0x04];
1599 	/* 0x0070 AFE_XCVR_EC_STS0 */
1600 	u32 afe_xcvr_error_capture_status0;
1601 	/* 0x0074 AFE_XCVR_EC_STS1 */
1602 	u32 afe_xcvr_error_capture_status1;
1603 	/* 0x0078 AFE_XCVR_EC_STS2 */
1604 	u32 afe_xcvr_error_capture_status2;
1605 	/* 0x007c afe_xcvr_ec_status3 */
1606 	u32 afe_xcvr_error_capture_status3;
1607 	/* 0x0080 AFE_XCVR_EC_STS4 */
1608 	u32 afe_xcvr_error_capture_status4;
1609 	/* 0x0084 AFE_XCVR_EC_STS5 */
1610 	u32 afe_xcvr_error_capture_status5;
1611 	/* 0x0088-0x00fc */
1612 	u32 reserved_008c_00fc[0x1e];
1613 };
1614 
1615 /**
1616  * struct scu_afe_registers - AFE Regsiters
1617  *
1618  *
1619  */
1620 /* Uaoa AFE registers */
1621 struct scu_afe_registers {
1622 	/* 0Xe000 AFE_BIAS_CTRL */
1623 	u32 afe_bias_control;
1624 	u32 reserved_0004;
1625 	/* 0x0008 AFE_PLL_CTRL0 */
1626 	u32 afe_pll_control0;
1627 	/* 0x000c AFE_PLL_CTRL1 */
1628 	u32 afe_pll_control1;
1629 	/* 0x0010 AFE_PLL_CTRL2 */
1630 	u32 afe_pll_control2;
1631 	/* 0x0014 AFE_CB_STS */
1632 	u32 afe_common_block_status;
1633 	/* 0x0018-0x007c */
1634 	u32 reserved_18_7c[0x1a];
1635 	/* 0x0080 AFE_PMSN_MCTRL0 */
1636 	u32 afe_pmsn_master_control0;
1637 	/* 0x0084 AFE_PMSN_MCTRL1 */
1638 	u32 afe_pmsn_master_control1;
1639 	/* 0x0088 AFE_PMSN_MCTRL2 */
1640 	u32 afe_pmsn_master_control2;
1641 	/* 0x008C-0x00fc */
1642 	u32 reserved_008c_00fc[0x1D];
1643 	/* 0x0100 AFE_DFX_MST_CTRL0 */
1644 	u32 afe_dfx_master_control0;
1645 	/* 0x0104 AFE_DFX_MST_CTRL1 */
1646 	u32 afe_dfx_master_control1;
1647 	/* 0x0108 AFE_DFX_DCL_CTRL */
1648 	u32 afe_dfx_dcl_control;
1649 	/* 0x010c AFE_DFX_DMON_CTRL */
1650 	u32 afe_dfx_digital_monitor_control;
1651 	/* 0x0110 AFE_DFX_AMONP_CTRL */
1652 	u32 afe_dfx_analog_p_monitor_control;
1653 	/* 0x0114 AFE_DFX_AMONN_CTRL */
1654 	u32 afe_dfx_analog_n_monitor_control;
1655 	/* 0x0118 AFE_DFX_NTL_STS */
1656 	u32 afe_dfx_ntl_status;
1657 	/* 0x011c AFE_DFX_FIFO_STS0 */
1658 	u32 afe_dfx_fifo_status0;
1659 	/* 0x0120 AFE_DFX_FIFO_STS1 */
1660 	u32 afe_dfx_fifo_status1;
1661 	/* 0x0124 AFE_DFX_MPAT_CTRL */
1662 	u32 afe_dfx_master_pattern_control;
1663 	/* 0x0128 AFE_DFX_P0_CTRL */
1664 	u32 afe_dfx_p0_control;
1665 	/* 0x012c-0x01a8 AFE_DFX_P0_DRx */
1666 	u32 afe_dfx_p0_data[32];
1667 	/* 0x01ac */
1668 	u32 reserved_01ac;
1669 	/* 0x01b0-0x020c AFE_DFX_P0_IRx */
1670 	u32 afe_dfx_p0_instruction[24];
1671 	/* 0x0210 */
1672 	u32 reserved_0210;
1673 	/* 0x0214 AFE_DFX_P1_CTRL */
1674 	u32 afe_dfx_p1_control;
1675 	/* 0x0218-0x245 AFE_DFX_P1_DRx */
1676 	u32 afe_dfx_p1_data[16];
1677 	/* 0x0258-0x029c */
1678 	u32 reserved_0258_029c[0x12];
1679 	/* 0x02a0-0x02bc AFE_DFX_P1_IRx */
1680 	u32 afe_dfx_p1_instruction[8];
1681 	/* 0x02c0-0x2fc */
1682 	u32 reserved_02c0_02fc[0x10];
1683 	/* 0x0300 AFE_DFX_TX_PMSN_CTRL */
1684 	u32 afe_dfx_tx_pmsn_control;
1685 	/* 0x0304 AFE_DFX_RX_PMSN_CTRL */
1686 	u32 afe_dfx_rx_pmsn_control;
1687 	u32 reserved_0308;
1688 	/* 0x030c AFE_DFX_NOA_CTRL0 */
1689 	u32 afe_dfx_noa_control0;
1690 	/* 0x0310 AFE_DFX_NOA_CTRL1 */
1691 	u32 afe_dfx_noa_control1;
1692 	/* 0x0314 AFE_DFX_NOA_CTRL2 */
1693 	u32 afe_dfx_noa_control2;
1694 	/* 0x0318 AFE_DFX_NOA_CTRL3 */
1695 	u32 afe_dfx_noa_control3;
1696 	/* 0x031c AFE_DFX_NOA_CTRL4 */
1697 	u32 afe_dfx_noa_control4;
1698 	/* 0x0320 AFE_DFX_NOA_CTRL5 */
1699 	u32 afe_dfx_noa_control5;
1700 	/* 0x0324 AFE_DFX_NOA_CTRL6 */
1701 	u32 afe_dfx_noa_control6;
1702 	/* 0x0328 AFE_DFX_NOA_CTRL7 */
1703 	u32 afe_dfx_noa_control7;
1704 	/* 0x032c-0x07fc */
1705 	u32 reserved_032c_07fc[0x135];
1706 
1707 	/* 0x0800-0x0bfc */
1708 	struct scu_afe_transceiver scu_afe_xcvr[4];
1709 
1710 	/* 0x0c00-0x0ffc */
1711 	u32 reserved_0c00_0ffc[0x0100];
1712 };
1713 
1714 struct scu_protocol_engine_group_registers {
1715 	u32 table[0xE0];
1716 };
1717 
1718 
1719 struct scu_viit_iit {
1720 	u32 table[256];
1721 };
1722 
1723 /**
1724  * Placeholder for the ZONE Partition Table information ZONING will not be
1725  *    included in the 1.1 release.
1726  *
1727  *
1728  */
1729 struct scu_zone_partition_table {
1730 	u32 table[2048];
1731 };
1732 
1733 /**
1734  * Placeholder for the CRAM register since I am not sure if we need to
1735  *    read/write to these registers as yet.
1736  *
1737  *
1738  */
1739 struct scu_completion_ram {
1740 	u32 ram[128];
1741 };
1742 
1743 /**
1744  * Placeholder for the FBRAM registers since I am not sure if we need to
1745  *    read/write to these registers as yet.
1746  *
1747  *
1748  */
1749 struct scu_frame_buffer_ram {
1750 	u32 ram[128];
1751 };
1752 
1753 #define scu_scratch_ram_SIZE_IN_DWORDS  256
1754 
1755 /**
1756  * Placeholder for the scratch RAM registers.
1757  *
1758  *
1759  */
1760 struct scu_scratch_ram {
1761 	u32 ram[scu_scratch_ram_SIZE_IN_DWORDS];
1762 };
1763 
1764 /**
1765  * Placeholder since I am not yet sure what these registers are here for.
1766  *
1767  *
1768  */
1769 struct noa_protocol_engine_partition {
1770 	u32 reserved[64];
1771 };
1772 
1773 /**
1774  * Placeholder since I am not yet sure what these registers are here for.
1775  *
1776  *
1777  */
1778 struct noa_hub_partition {
1779 	u32 reserved[64];
1780 };
1781 
1782 /**
1783  * Placeholder since I am not yet sure what these registers are here for.
1784  *
1785  *
1786  */
1787 struct noa_host_interface_partition {
1788 	u32 reserved[64];
1789 };
1790 
1791 /**
1792  * struct transport_link_layer_pair - The SCU Hardware pairs up the TL
1793  *    registers with the LL registers so we must place them adjcent to make the
1794  *    array of registers in the PEG.
1795  *
1796  *
1797  */
1798 struct transport_link_layer_pair {
1799 	struct scu_transport_layer_registers tl;
1800 	struct scu_link_layer_registers ll;
1801 };
1802 
1803 /**
1804  * struct scu_peg_registers - SCU Protocol Engine Memory mapped register space.
1805  *     These registers are unique to each protocol engine group.  There can be
1806  *    at most two PEG for a single SCU part.
1807  *
1808  *
1809  */
1810 struct scu_peg_registers {
1811 	struct transport_link_layer_pair pe[4];
1812 	struct scu_port_task_scheduler_group_registers ptsg;
1813 	struct scu_protocol_engine_group_registers peg;
1814 	struct scu_sgpio_registers sgpio;
1815 	u32 reserved_01500_1BFF[0x1C0];
1816 	struct scu_viit_entry viit[64];
1817 	struct scu_zone_partition_table zpt0;
1818 	struct scu_zone_partition_table zpt1;
1819 };
1820 
1821 /**
1822  * struct scu_registers - SCU regsiters including both PEG registers if we turn
1823  *    on that compile option. All of these registers are in the memory mapped
1824  *    space returned from BAR1.
1825  *
1826  *
1827  */
1828 struct scu_registers {
1829 	/* 0x0000 - PEG 0 */
1830 	struct scu_peg_registers peg0;
1831 
1832 	/* 0x6000 - SDMA and Miscellaneous */
1833 	struct scu_sdma_registers sdma;
1834 	struct scu_completion_ram cram;
1835 	struct scu_frame_buffer_ram fbram;
1836 	u32 reserved_6800_69FF[0x80];
1837 	struct noa_protocol_engine_partition noa_pe;
1838 	struct noa_hub_partition noa_hub;
1839 	struct noa_host_interface_partition noa_if;
1840 	u32 reserved_6d00_7fff[0x4c0];
1841 
1842 	/* 0x8000 - PEG 1 */
1843 	struct scu_peg_registers peg1;
1844 
1845 	/* 0xE000 - AFE Registers */
1846 	struct scu_afe_registers afe;
1847 
1848 	/* 0xF000 - reserved */
1849 	u32 reserved_f000_211fff[0x80c00];
1850 
1851 	/* 0x212000 - scratch RAM */
1852 	struct scu_scratch_ram scratch_ram;
1853 };
1854 
1855 #endif   /* _SCU_REGISTERS_HEADER_ */
1856