1 /* 2 * SDIO Host Controller Spec header file 3 * Register map and definitions for the Standard Host Controller 4 * 5 * Copyright (C) 1999-2013, Broadcom Corporation 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * $Id: sdioh.h 345499 2012-07-18 06:59:05Z $ 26 */ 27 28 #ifndef _SDIOH_H 29 #define _SDIOH_H 30 31 #define SD_SysAddr 0x000 32 #define SD_BlockSize 0x004 33 #define SD_BlockCount 0x006 34 #define SD_Arg0 0x008 35 #define SD_Arg1 0x00A 36 #define SD_TransferMode 0x00C 37 #define SD_Command 0x00E 38 #define SD_Response0 0x010 39 #define SD_Response1 0x012 40 #define SD_Response2 0x014 41 #define SD_Response3 0x016 42 #define SD_Response4 0x018 43 #define SD_Response5 0x01A 44 #define SD_Response6 0x01C 45 #define SD_Response7 0x01E 46 #define SD_BufferDataPort0 0x020 47 #define SD_BufferDataPort1 0x022 48 #define SD_PresentState 0x024 49 #define SD_HostCntrl 0x028 50 #define SD_PwrCntrl 0x029 51 #define SD_BlockGapCntrl 0x02A 52 #define SD_WakeupCntrl 0x02B 53 #define SD_ClockCntrl 0x02C 54 #define SD_TimeoutCntrl 0x02E 55 #define SD_SoftwareReset 0x02F 56 #define SD_IntrStatus 0x030 57 #define SD_ErrorIntrStatus 0x032 58 #define SD_IntrStatusEnable 0x034 59 #define SD_ErrorIntrStatusEnable 0x036 60 #define SD_IntrSignalEnable 0x038 61 #define SD_ErrorIntrSignalEnable 0x03A 62 #define SD_CMD12ErrorStatus 0x03C 63 #define SD_Capabilities 0x040 64 #define SD_Capabilities3 0x044 65 #define SD_MaxCurCap 0x048 66 #define SD_MaxCurCap_Reserved 0x04C 67 #define SD_ADMA_ErrStatus 0x054 68 #define SD_ADMA_SysAddr 0x58 69 #define SD_SlotInterruptStatus 0x0FC 70 #define SD_HostControllerVersion 0x0FE 71 #define SD_GPIO_Reg 0x100 72 #define SD_GPIO_OE 0x104 73 #define SD_GPIO_Enable 0x108 74 75 /* SD specific registers in PCI config space */ 76 #define SD_SlotInfo 0x40 77 78 /* HC 3.0 specific registers and offsets */ 79 #define SD3_HostCntrl2 0x03E 80 /* preset regsstart and count */ 81 #define SD3_PresetValStart 0x060 82 #define SD3_PresetValCount 8 83 /* preset-indiv regs */ 84 #define SD3_PresetVal_init 0x060 85 #define SD3_PresetVal_default 0x062 86 #define SD3_PresetVal_HS 0x064 87 #define SD3_PresetVal_SDR12 0x066 88 #define SD3_PresetVal_SDR25 0x068 89 #define SD3_PresetVal_SDR50 0x06a 90 #define SD3_PresetVal_SDR104 0x06c 91 #define SD3_PresetVal_DDR50 0x06e 92 /* SDIO3.0 Revx specific Registers */ 93 #define SD3_Tuning_Info_Register 0x0EC 94 #define SD3_WL_BT_reset_register 0x0F0 95 96 97 /* preset value indices */ 98 #define SD3_PRESETVAL_INITIAL_IX 0 99 #define SD3_PRESETVAL_DESPEED_IX 1 100 #define SD3_PRESETVAL_HISPEED_IX 2 101 #define SD3_PRESETVAL_SDR12_IX 3 102 #define SD3_PRESETVAL_SDR25_IX 4 103 #define SD3_PRESETVAL_SDR50_IX 5 104 #define SD3_PRESETVAL_SDR104_IX 6 105 #define SD3_PRESETVAL_DDR50_IX 7 106 107 /* SD_Capabilities reg (0x040) */ 108 #define CAP_TO_CLKFREQ_M BITFIELD_MASK(6) 109 #define CAP_TO_CLKFREQ_S 0 110 #define CAP_TO_CLKUNIT_M BITFIELD_MASK(1) 111 #define CAP_TO_CLKUNIT_S 7 112 /* Note: for sdio-2.0 case, this mask has to be 6 bits, but msb 2 113 bits are reserved. going ahead with 8 bits, as it is req for 3.0 114 */ 115 #define CAP_BASECLK_M BITFIELD_MASK(8) 116 #define CAP_BASECLK_S 8 117 #define CAP_MAXBLOCK_M BITFIELD_MASK(2) 118 #define CAP_MAXBLOCK_S 16 119 #define CAP_ADMA2_M BITFIELD_MASK(1) 120 #define CAP_ADMA2_S 19 121 #define CAP_ADMA1_M BITFIELD_MASK(1) 122 #define CAP_ADMA1_S 20 123 #define CAP_HIGHSPEED_M BITFIELD_MASK(1) 124 #define CAP_HIGHSPEED_S 21 125 #define CAP_DMA_M BITFIELD_MASK(1) 126 #define CAP_DMA_S 22 127 #define CAP_SUSPEND_M BITFIELD_MASK(1) 128 #define CAP_SUSPEND_S 23 129 #define CAP_VOLT_3_3_M BITFIELD_MASK(1) 130 #define CAP_VOLT_3_3_S 24 131 #define CAP_VOLT_3_0_M BITFIELD_MASK(1) 132 #define CAP_VOLT_3_0_S 25 133 #define CAP_VOLT_1_8_M BITFIELD_MASK(1) 134 #define CAP_VOLT_1_8_S 26 135 #define CAP_64BIT_HOST_M BITFIELD_MASK(1) 136 #define CAP_64BIT_HOST_S 28 137 138 #define SDIO_OCR_READ_FAIL (2) 139 140 141 #define CAP_ASYNCINT_SUP_M BITFIELD_MASK(1) 142 #define CAP_ASYNCINT_SUP_S 29 143 144 #define CAP_SLOTTYPE_M BITFIELD_MASK(2) 145 #define CAP_SLOTTYPE_S 30 146 147 #define CAP3_MSBits_OFFSET (32) 148 /* note: following are caps MSB32 bits. 149 So the bits start from 0, instead of 32. that is why 150 CAP3_MSBits_OFFSET is subtracted. 151 */ 152 #define CAP3_SDR50_SUP_M BITFIELD_MASK(1) 153 #define CAP3_SDR50_SUP_S (32 - CAP3_MSBits_OFFSET) 154 155 #define CAP3_SDR104_SUP_M BITFIELD_MASK(1) 156 #define CAP3_SDR104_SUP_S (33 - CAP3_MSBits_OFFSET) 157 158 #define CAP3_DDR50_SUP_M BITFIELD_MASK(1) 159 #define CAP3_DDR50_SUP_S (34 - CAP3_MSBits_OFFSET) 160 161 /* for knowing the clk caps in a single read */ 162 #define CAP3_30CLKCAP_M BITFIELD_MASK(3) 163 #define CAP3_30CLKCAP_S (32 - CAP3_MSBits_OFFSET) 164 165 #define CAP3_DRIVTYPE_A_M BITFIELD_MASK(1) 166 #define CAP3_DRIVTYPE_A_S (36 - CAP3_MSBits_OFFSET) 167 168 #define CAP3_DRIVTYPE_C_M BITFIELD_MASK(1) 169 #define CAP3_DRIVTYPE_C_S (37 - CAP3_MSBits_OFFSET) 170 171 #define CAP3_DRIVTYPE_D_M BITFIELD_MASK(1) 172 #define CAP3_DRIVTYPE_D_S (38 - CAP3_MSBits_OFFSET) 173 174 #define CAP3_RETUNING_TC_M BITFIELD_MASK(4) 175 #define CAP3_RETUNING_TC_S (40 - CAP3_MSBits_OFFSET) 176 177 #define CAP3_TUNING_SDR50_M BITFIELD_MASK(1) 178 #define CAP3_TUNING_SDR50_S (45 - CAP3_MSBits_OFFSET) 179 180 #define CAP3_RETUNING_MODES_M BITFIELD_MASK(2) 181 #define CAP3_RETUNING_MODES_S (46 - CAP3_MSBits_OFFSET) 182 183 #define CAP3_CLK_MULT_M BITFIELD_MASK(8) 184 #define CAP3_CLK_MULT_S (48 - CAP3_MSBits_OFFSET) 185 186 #define PRESET_DRIVR_SELECT_M BITFIELD_MASK(2) 187 #define PRESET_DRIVR_SELECT_S 14 188 189 #define PRESET_CLK_DIV_M BITFIELD_MASK(10) 190 #define PRESET_CLK_DIV_S 0 191 192 /* SD_MaxCurCap reg (0x048) */ 193 #define CAP_CURR_3_3_M BITFIELD_MASK(8) 194 #define CAP_CURR_3_3_S 0 195 #define CAP_CURR_3_0_M BITFIELD_MASK(8) 196 #define CAP_CURR_3_0_S 8 197 #define CAP_CURR_1_8_M BITFIELD_MASK(8) 198 #define CAP_CURR_1_8_S 16 199 200 /* SD_SysAddr: Offset 0x0000, Size 4 bytes */ 201 202 /* SD_BlockSize: Offset 0x004, Size 2 bytes */ 203 #define BLKSZ_BLKSZ_M BITFIELD_MASK(12) 204 #define BLKSZ_BLKSZ_S 0 205 #define BLKSZ_BNDRY_M BITFIELD_MASK(3) 206 #define BLKSZ_BNDRY_S 12 207 208 /* SD_BlockCount: Offset 0x006, size 2 bytes */ 209 210 /* SD_Arg0: Offset 0x008, size = 4 bytes */ 211 /* SD_TransferMode Offset 0x00C, size = 2 bytes */ 212 #define XFER_DMA_ENABLE_M BITFIELD_MASK(1) 213 #define XFER_DMA_ENABLE_S 0 214 #define XFER_BLK_COUNT_EN_M BITFIELD_MASK(1) 215 #define XFER_BLK_COUNT_EN_S 1 216 #define XFER_CMD_12_EN_M BITFIELD_MASK(1) 217 #define XFER_CMD_12_EN_S 2 218 #define XFER_DATA_DIRECTION_M BITFIELD_MASK(1) 219 #define XFER_DATA_DIRECTION_S 4 220 #define XFER_MULTI_BLOCK_M BITFIELD_MASK(1) 221 #define XFER_MULTI_BLOCK_S 5 222 223 /* SD_Command: Offset 0x00E, size = 2 bytes */ 224 /* resp_type field */ 225 #define RESP_TYPE_NONE 0 226 #define RESP_TYPE_136 1 227 #define RESP_TYPE_48 2 228 #define RESP_TYPE_48_BUSY 3 229 /* type field */ 230 #define CMD_TYPE_NORMAL 0 231 #define CMD_TYPE_SUSPEND 1 232 #define CMD_TYPE_RESUME 2 233 #define CMD_TYPE_ABORT 3 234 235 #define CMD_RESP_TYPE_M BITFIELD_MASK(2) /* Bits [0-1] - Response type */ 236 #define CMD_RESP_TYPE_S 0 237 #define CMD_CRC_EN_M BITFIELD_MASK(1) /* Bit 3 - CRC enable */ 238 #define CMD_CRC_EN_S 3 239 #define CMD_INDEX_EN_M BITFIELD_MASK(1) /* Bit 4 - Enable index checking */ 240 #define CMD_INDEX_EN_S 4 241 #define CMD_DATA_EN_M BITFIELD_MASK(1) /* Bit 5 - Using DAT line */ 242 #define CMD_DATA_EN_S 5 243 #define CMD_TYPE_M BITFIELD_MASK(2) /* Bit [6-7] - Normal, abort, resume, etc 244 */ 245 #define CMD_TYPE_S 6 246 #define CMD_INDEX_M BITFIELD_MASK(6) /* Bits [8-13] - Command number */ 247 #define CMD_INDEX_S 8 248 249 /* SD_BufferDataPort0 : Offset 0x020, size = 2 or 4 bytes */ 250 /* SD_BufferDataPort1 : Offset 0x022, size = 2 bytes */ 251 /* SD_PresentState : Offset 0x024, size = 4 bytes */ 252 #define PRES_CMD_INHIBIT_M BITFIELD_MASK(1) /* Bit 0 May use CMD */ 253 #define PRES_CMD_INHIBIT_S 0 254 #define PRES_DAT_INHIBIT_M BITFIELD_MASK(1) /* Bit 1 May use DAT */ 255 #define PRES_DAT_INHIBIT_S 1 256 #define PRES_DAT_BUSY_M BITFIELD_MASK(1) /* Bit 2 DAT is busy */ 257 #define PRES_DAT_BUSY_S 2 258 #define PRES_PRESENT_RSVD_M BITFIELD_MASK(5) /* Bit [3-7] rsvd */ 259 #define PRES_PRESENT_RSVD_S 3 260 #define PRES_WRITE_ACTIVE_M BITFIELD_MASK(1) /* Bit 8 Write is active */ 261 #define PRES_WRITE_ACTIVE_S 8 262 #define PRES_READ_ACTIVE_M BITFIELD_MASK(1) /* Bit 9 Read is active */ 263 #define PRES_READ_ACTIVE_S 9 264 #define PRES_WRITE_DATA_RDY_M BITFIELD_MASK(1) /* Bit 10 Write buf is avail */ 265 #define PRES_WRITE_DATA_RDY_S 10 266 #define PRES_READ_DATA_RDY_M BITFIELD_MASK(1) /* Bit 11 Read buf data avail */ 267 #define PRES_READ_DATA_RDY_S 11 268 #define PRES_CARD_PRESENT_M BITFIELD_MASK(1) /* Bit 16 Card present - debounced */ 269 #define PRES_CARD_PRESENT_S 16 270 #define PRES_CARD_STABLE_M BITFIELD_MASK(1) /* Bit 17 Debugging */ 271 #define PRES_CARD_STABLE_S 17 272 #define PRES_CARD_PRESENT_RAW_M BITFIELD_MASK(1) /* Bit 18 Not debounced */ 273 #define PRES_CARD_PRESENT_RAW_S 18 274 #define PRES_WRITE_ENABLED_M BITFIELD_MASK(1) /* Bit 19 Write protected? */ 275 #define PRES_WRITE_ENABLED_S 19 276 #define PRES_DAT_SIGNAL_M BITFIELD_MASK(4) /* Bit [20-23] Debugging */ 277 #define PRES_DAT_SIGNAL_S 20 278 #define PRES_CMD_SIGNAL_M BITFIELD_MASK(1) /* Bit 24 Debugging */ 279 #define PRES_CMD_SIGNAL_S 24 280 281 /* SD_HostCntrl: Offset 0x028, size = 1 bytes */ 282 #define HOST_LED_M BITFIELD_MASK(1) /* Bit 0 LED On/Off */ 283 #define HOST_LED_S 0 284 #define HOST_DATA_WIDTH_M BITFIELD_MASK(1) /* Bit 1 4 bit enable */ 285 #define HOST_DATA_WIDTH_S 1 286 #define HOST_HI_SPEED_EN_M BITFIELD_MASK(1) /* Bit 2 High speed vs low speed */ 287 #define HOST_DMA_SEL_S 3 288 #define HOST_DMA_SEL_M BITFIELD_MASK(2) /* Bit 4:3 DMA Select */ 289 #define HOST_HI_SPEED_EN_S 2 290 291 /* Host Control2: */ 292 #define HOSTCtrl2_PRESVAL_EN_M BITFIELD_MASK(1) /* 1 bit */ 293 #define HOSTCtrl2_PRESVAL_EN_S 15 /* bit# */ 294 295 #define HOSTCtrl2_ASYINT_EN_M BITFIELD_MASK(1) /* 1 bit */ 296 #define HOSTCtrl2_ASYINT_EN_S 14 /* bit# */ 297 298 #define HOSTCtrl2_SAMPCLK_SEL_M BITFIELD_MASK(1) /* 1 bit */ 299 #define HOSTCtrl2_SAMPCLK_SEL_S 7 /* bit# */ 300 301 #define HOSTCtrl2_EXEC_TUNING_M BITFIELD_MASK(1) /* 1 bit */ 302 #define HOSTCtrl2_EXEC_TUNING_S 6 /* bit# */ 303 304 #define HOSTCtrl2_DRIVSTRENGTH_SEL_M BITFIELD_MASK(2) /* 2 bit */ 305 #define HOSTCtrl2_DRIVSTRENGTH_SEL_S 4 /* bit# */ 306 307 #define HOSTCtrl2_1_8SIG_EN_M BITFIELD_MASK(1) /* 1 bit */ 308 #define HOSTCtrl2_1_8SIG_EN_S 3 /* bit# */ 309 310 #define HOSTCtrl2_UHSMODE_SEL_M BITFIELD_MASK(3) /* 3 bit */ 311 #define HOSTCtrl2_UHSMODE_SEL_S 0 /* bit# */ 312 313 #define HOST_CONTR_VER_2 (1) 314 #define HOST_CONTR_VER_3 (2) 315 316 /* misc defines */ 317 #define SD1_MODE 0x1 /* SD Host Cntrlr Spec */ 318 #define SD4_MODE 0x2 /* SD Host Cntrlr Spec */ 319 320 /* SD_PwrCntrl: Offset 0x029, size = 1 bytes */ 321 #define PWR_BUS_EN_M BITFIELD_MASK(1) /* Bit 0 Power the bus */ 322 #define PWR_BUS_EN_S 0 323 #define PWR_VOLTS_M BITFIELD_MASK(3) /* Bit [1-3] Voltage Select */ 324 #define PWR_VOLTS_S 1 325 326 /* SD_SoftwareReset: Offset 0x02F, size = 1 byte */ 327 #define SW_RESET_ALL_M BITFIELD_MASK(1) /* Bit 0 Reset All */ 328 #define SW_RESET_ALL_S 0 329 #define SW_RESET_CMD_M BITFIELD_MASK(1) /* Bit 1 CMD Line Reset */ 330 #define SW_RESET_CMD_S 1 331 #define SW_RESET_DAT_M BITFIELD_MASK(1) /* Bit 2 DAT Line Reset */ 332 #define SW_RESET_DAT_S 2 333 334 /* SD_IntrStatus: Offset 0x030, size = 2 bytes */ 335 /* Defs also serve SD_IntrStatusEnable and SD_IntrSignalEnable */ 336 #define INTSTAT_CMD_COMPLETE_M BITFIELD_MASK(1) /* Bit 0 */ 337 #define INTSTAT_CMD_COMPLETE_S 0 338 #define INTSTAT_XFER_COMPLETE_M BITFIELD_MASK(1) 339 #define INTSTAT_XFER_COMPLETE_S 1 340 #define INTSTAT_BLOCK_GAP_EVENT_M BITFIELD_MASK(1) 341 #define INTSTAT_BLOCK_GAP_EVENT_S 2 342 #define INTSTAT_DMA_INT_M BITFIELD_MASK(1) 343 #define INTSTAT_DMA_INT_S 3 344 #define INTSTAT_BUF_WRITE_READY_M BITFIELD_MASK(1) 345 #define INTSTAT_BUF_WRITE_READY_S 4 346 #define INTSTAT_BUF_READ_READY_M BITFIELD_MASK(1) 347 #define INTSTAT_BUF_READ_READY_S 5 348 #define INTSTAT_CARD_INSERTION_M BITFIELD_MASK(1) 349 #define INTSTAT_CARD_INSERTION_S 6 350 #define INTSTAT_CARD_REMOVAL_M BITFIELD_MASK(1) 351 #define INTSTAT_CARD_REMOVAL_S 7 352 #define INTSTAT_CARD_INT_M BITFIELD_MASK(1) 353 #define INTSTAT_CARD_INT_S 8 354 #define INTSTAT_RETUNING_INT_M BITFIELD_MASK(1) /* Bit 12 */ 355 #define INTSTAT_RETUNING_INT_S 12 356 #define INTSTAT_ERROR_INT_M BITFIELD_MASK(1) /* Bit 15 */ 357 #define INTSTAT_ERROR_INT_S 15 358 359 /* SD_ErrorIntrStatus: Offset 0x032, size = 2 bytes */ 360 /* Defs also serve SD_ErrorIntrStatusEnable and SD_ErrorIntrSignalEnable */ 361 #define ERRINT_CMD_TIMEOUT_M BITFIELD_MASK(1) 362 #define ERRINT_CMD_TIMEOUT_S 0 363 #define ERRINT_CMD_CRC_M BITFIELD_MASK(1) 364 #define ERRINT_CMD_CRC_S 1 365 #define ERRINT_CMD_ENDBIT_M BITFIELD_MASK(1) 366 #define ERRINT_CMD_ENDBIT_S 2 367 #define ERRINT_CMD_INDEX_M BITFIELD_MASK(1) 368 #define ERRINT_CMD_INDEX_S 3 369 #define ERRINT_DATA_TIMEOUT_M BITFIELD_MASK(1) 370 #define ERRINT_DATA_TIMEOUT_S 4 371 #define ERRINT_DATA_CRC_M BITFIELD_MASK(1) 372 #define ERRINT_DATA_CRC_S 5 373 #define ERRINT_DATA_ENDBIT_M BITFIELD_MASK(1) 374 #define ERRINT_DATA_ENDBIT_S 6 375 #define ERRINT_CURRENT_LIMIT_M BITFIELD_MASK(1) 376 #define ERRINT_CURRENT_LIMIT_S 7 377 #define ERRINT_AUTO_CMD12_M BITFIELD_MASK(1) 378 #define ERRINT_AUTO_CMD12_S 8 379 #define ERRINT_VENDOR_M BITFIELD_MASK(4) 380 #define ERRINT_VENDOR_S 12 381 #define ERRINT_ADMA_M BITFIELD_MASK(1) 382 #define ERRINT_ADMA_S 9 383 384 /* Also provide definitions in "normal" form to allow combined masks */ 385 #define ERRINT_CMD_TIMEOUT_BIT 0x0001 386 #define ERRINT_CMD_CRC_BIT 0x0002 387 #define ERRINT_CMD_ENDBIT_BIT 0x0004 388 #define ERRINT_CMD_INDEX_BIT 0x0008 389 #define ERRINT_DATA_TIMEOUT_BIT 0x0010 390 #define ERRINT_DATA_CRC_BIT 0x0020 391 #define ERRINT_DATA_ENDBIT_BIT 0x0040 392 #define ERRINT_CURRENT_LIMIT_BIT 0x0080 393 #define ERRINT_AUTO_CMD12_BIT 0x0100 394 #define ERRINT_ADMA_BIT 0x0200 395 396 /* Masks to select CMD vs. DATA errors */ 397 #define ERRINT_CMD_ERRS (ERRINT_CMD_TIMEOUT_BIT | ERRINT_CMD_CRC_BIT |\ 398 ERRINT_CMD_ENDBIT_BIT | ERRINT_CMD_INDEX_BIT) 399 #define ERRINT_DATA_ERRS (ERRINT_DATA_TIMEOUT_BIT | ERRINT_DATA_CRC_BIT |\ 400 ERRINT_DATA_ENDBIT_BIT | ERRINT_ADMA_BIT) 401 #define ERRINT_TRANSFER_ERRS (ERRINT_CMD_ERRS | ERRINT_DATA_ERRS) 402 403 /* SD_WakeupCntr_BlockGapCntrl : Offset 0x02A , size = bytes */ 404 /* SD_ClockCntrl : Offset 0x02C , size = bytes */ 405 /* SD_SoftwareReset_TimeoutCntrl : Offset 0x02E , size = bytes */ 406 /* SD_IntrStatus : Offset 0x030 , size = bytes */ 407 /* SD_ErrorIntrStatus : Offset 0x032 , size = bytes */ 408 /* SD_IntrStatusEnable : Offset 0x034 , size = bytes */ 409 /* SD_ErrorIntrStatusEnable : Offset 0x036 , size = bytes */ 410 /* SD_IntrSignalEnable : Offset 0x038 , size = bytes */ 411 /* SD_ErrorIntrSignalEnable : Offset 0x03A , size = bytes */ 412 /* SD_CMD12ErrorStatus : Offset 0x03C , size = bytes */ 413 /* SD_Capabilities : Offset 0x040 , size = bytes */ 414 /* SD_MaxCurCap : Offset 0x048 , size = bytes */ 415 /* SD_MaxCurCap_Reserved: Offset 0x04C , size = bytes */ 416 /* SD_SlotInterruptStatus: Offset 0x0FC , size = bytes */ 417 /* SD_HostControllerVersion : Offset 0x0FE , size = bytes */ 418 419 /* SDIO Host Control Register DMA Mode Definitions */ 420 #define SDIOH_SDMA_MODE 0 421 #define SDIOH_ADMA1_MODE 1 422 #define SDIOH_ADMA2_MODE 2 423 #define SDIOH_ADMA2_64_MODE 3 424 425 #define ADMA2_ATTRIBUTE_VALID (1 << 0) /* ADMA Descriptor line valid */ 426 #define ADMA2_ATTRIBUTE_END (1 << 1) /* End of Descriptor */ 427 #define ADMA2_ATTRIBUTE_INT (1 << 2) /* Interrupt when line is done */ 428 #define ADMA2_ATTRIBUTE_ACT_NOP (0 << 4) /* Skip current line, go to next. */ 429 #define ADMA2_ATTRIBUTE_ACT_RSV (1 << 4) /* Same as NOP */ 430 #define ADMA1_ATTRIBUTE_ACT_SET (1 << 4) /* ADMA1 Only - set transfer length */ 431 #define ADMA2_ATTRIBUTE_ACT_TRAN (2 << 4) /* Transfer Data of one descriptor line. */ 432 #define ADMA2_ATTRIBUTE_ACT_LINK (3 << 4) /* Link Descriptor */ 433 434 /* ADMA2 Descriptor Table Entry for 32-bit Address */ 435 typedef struct adma2_dscr_32b { 436 uint32 len_attr; 437 uint32 phys_addr; 438 } adma2_dscr_32b_t; 439 440 /* ADMA1 Descriptor Table Entry */ 441 typedef struct adma1_dscr { 442 uint32 phys_addr_attr; 443 } adma1_dscr_t; 444 445 #endif /* _SDIOH_H */ 446