Searched refs:UART_LSR_THRE (Results 1 – 25 of 25) sorted by relevance
103 #define UART_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)126 #define UART_LSR_THRE 0x01 /* Transmit-hold-register empty */ macro
63 wait_for_bits(up, UART_LSR_THRE); in nwpserial_console_putchar()87 while ((dcr_read(up->dcr_host, UART_LSR) & UART_LSR_THRE) == 0) in nwpserial_console_write()256 wait_for_bits(up, UART_LSR_THRE); in nwpserial_putchar()
263 if (lsr & UART_LSR_THRE) in serial_pxa_irq()518 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; in serial_pxa_set_termios()624 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
443 if (lsr & UART_LSR_THRE) in siu_interrupt()561 port->read_status_mask = UART_LSR_THRE | UART_LSR_OE | UART_LSR_DR; in siu_set_termios()738 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
464 if (status & UART_LSR_THRE) in sunsu_serial_interrupt()834 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; in sunsu_change_speed()987 } while (!(lsr & UART_LSR_THRE)); in sunsu_serio_write()1248 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
421 if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI)) in serial_omap_irq()768 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; in serial_omap_set_termios()980 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)1528 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & in serial_omap_mdr1_errataset()1529 (UART_LSR_THRE | UART_LSR_DR))) { in serial_omap_mdr1_errataset()
622 if (lsr & UART_LSR_THRE) in port_irq()971 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; in serial_hsu_set_termios()1065 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
417 while (!(serial_in(up, UART_LSR) & UART_LSR_THRE)); in transmit_chars()752 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; in m32r_sio_set_termios()
207 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)1546 wait_for_xmitr(priv, UART_LSR_THRE); in pch_console_putchar()
376 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) in neo_copy_data_from_uart_to_queue()434 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) { in neo_copy_data_from_uart_to_queue()435 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR); in neo_copy_data_from_uart_to_queue()520 if (ch->ch_cached_lsr & UART_LSR_THRE) { in neo_copy_data_from_queue_to_uart()521 ch->ch_cached_lsr &= ~(UART_LSR_THRE); in neo_copy_data_from_queue_to_uart()911 if (linestatus & UART_LSR_THRE) { in neo_parse_lsr()
36 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
57 if (lsr & UART_LSR_THRE) in fsl8250_handle_irq()
85 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)1296 (lsr & UART_LSR_THRE) : in serial8250_start_tx()1532 if (status & UART_LSR_THRE) in serial8250_handle_irq()1748 (lsr & UART_LSR_THRE)) { in serial8250_backup_timeout()2023 wait_for_xmitr(up, UART_LSR_THRE); in serial8250_startup()2315 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; in serial8250_do_set_termios()2790 wait_for_xmitr(up, UART_LSR_THRE); in serial8250_console_putchar()
80 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
115 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) in dtl1_write()319 if (lsr & UART_LSR_THRE) { in dtl1_interrupt()
116 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) in btuart_write()318 if (lsr & UART_LSR_THRE) { in btuart_interrupt()
628 if (lsr & UART_LSR_THRE) /* FIFO is empty */ in sir_interrupt()751 while (!(inb(io + UART_LSR) & UART_LSR_THRE)) in send_pulse()
452 while (!(sinp(UART_LSR) & UART_LSR_THRE)) in send_pulse_irdeo()
322 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; in sdio_uart_change_speed()568 if (lsr & UART_LSR_THRE) in sdio_uart_irq()
761 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; in mxser_change_speed()1748 lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_THRE; in mxser_ioctl()2290 UART_LSR_THRE)) in mxser_interrupt()2293 if (status & UART_LSR_THRE) in mxser_interrupt()
850 if (lsr & UART_LSR_THRE) in ali_ircc_sir_interrupt()1315 if (!(inb(iobase+UART_LSR) & UART_LSR_THRE)) { in ali_ircc_sir_write()
1610 if (lsr & UART_LSR_THRE) in smsc_ircc_interrupt_sir()2033 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) { in smsc_ircc_sir_write()
404 if (status & UART_LSR_THRE) in rs_interrupt_elsa()
1825 if ((data & (UART_LSR_TEMT | UART_LSR_THRE)) in get_lsr_info()1826 == (UART_LSR_TEMT | UART_LSR_THRE)) { in get_lsr_info()
1106 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ macro