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Searched refs:ah (Results 1 – 25 of 139) sorted by relevance

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/drivers/net/wireless/ath/ath9k/
Dhw.c28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
49 static void ath9k_hw_init_cal_settings(struct ath_hw *ah) in ath9k_hw_init_cal_settings() argument
51 ath9k_hw_private_ops(ah)->init_cal_settings(ah); in ath9k_hw_init_cal_settings()
54 static void ath9k_hw_init_mode_regs(struct ath_hw *ah) in ath9k_hw_init_mode_regs() argument
56 ath9k_hw_private_ops(ah)->init_mode_regs(ah); in ath9k_hw_init_mode_regs()
59 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, in ath9k_hw_compute_pll_control() argument
62 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); in ath9k_hw_compute_pll_control()
65 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) in ath9k_hw_init_mode_gain_regs() argument
67 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) in ath9k_hw_init_mode_gain_regs()
70 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); in ath9k_hw_init_mode_gain_regs()
[all …]
Dar9002_calib.c29 static bool ar9002_hw_is_cal_supported(struct ath_hw *ah, in ar9002_hw_is_cal_supported() argument
34 switch (ah->supp_cals & cal_type) { in ar9002_hw_is_cal_supported()
44 !((IS_CHAN_2GHZ(chan) || IS_CHAN_A_FAST_CLOCK(ah, chan)) && in ar9002_hw_is_cal_supported()
52 static void ar9002_hw_setup_calibration(struct ath_hw *ah, in ar9002_hw_setup_calibration() argument
55 struct ath_common *common = ath9k_hw_common(ah); in ar9002_hw_setup_calibration()
57 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
63 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9002_hw_setup_calibration()
68 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); in ar9002_hw_setup_calibration()
72 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); in ar9002_hw_setup_calibration()
77 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
[all …]
Dar9003_hw.c34 static void ar9003_hw_init_mode_regs(struct ath_hw *ah) in ar9003_hw_init_mode_regs() argument
44 if (AR_SREV_9330_11(ah)) { in ar9003_hw_init_mode_regs()
46 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); in ar9003_hw_init_mode_regs()
47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], in ar9003_hw_init_mode_regs()
50 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], in ar9003_hw_init_mode_regs()
55 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); in ar9003_hw_init_mode_regs()
56 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], in ar9003_hw_init_mode_regs()
59 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], in ar9003_hw_init_mode_regs()
64 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); in ar9003_hw_init_mode_regs()
65 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], in ar9003_hw_init_mode_regs()
[all …]
Dar9002_hw.c30 static void ar9002_hw_init_mode_regs(struct ath_hw *ah) in ar9002_hw_init_mode_regs() argument
32 if (AR_SREV_9271(ah)) { in ar9002_hw_init_mode_regs()
33 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271, in ar9002_hw_init_mode_regs()
35 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, in ar9002_hw_init_mode_regs()
37 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg, in ar9002_hw_init_mode_regs()
42 if (ah->config.pcie_clock_req) in ar9002_hw_init_mode_regs()
43 INIT_INI_ARRAY(&ah->iniPcieSerdes, in ar9002_hw_init_mode_regs()
47 INIT_INI_ARRAY(&ah->iniPcieSerdes, in ar9002_hw_init_mode_regs()
51 if (AR_SREV_9287_11_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
52 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, in ar9002_hw_init_mode_regs()
[all …]
Dhw-ops.h24 static inline void ath9k_hw_configpcipowersave(struct ath_hw *ah, in ath9k_hw_configpcipowersave() argument
27 if (!ah->aspm_enabled) in ath9k_hw_configpcipowersave()
30 ath9k_hw_ops(ah)->config_pci_powersave(ah, power_off); in ath9k_hw_configpcipowersave()
33 static inline void ath9k_hw_rxena(struct ath_hw *ah) in ath9k_hw_rxena() argument
35 ath9k_hw_ops(ah)->rx_enable(ah); in ath9k_hw_rxena()
38 static inline void ath9k_hw_set_desc_link(struct ath_hw *ah, void *ds, in ath9k_hw_set_desc_link() argument
41 ath9k_hw_ops(ah)->set_desc_link(ds, link); in ath9k_hw_set_desc_link()
44 static inline bool ath9k_hw_calibrate(struct ath_hw *ah, in ath9k_hw_calibrate() argument
49 return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal); in ath9k_hw_calibrate()
52 static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) in ath9k_hw_getisr() argument
[all …]
Dani.c107 static bool use_new_ani(struct ath_hw *ah) in use_new_ani() argument
109 return AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani; in use_new_ani()
112 static void ath9k_hw_update_mibstats(struct ath_hw *ah, in ath9k_hw_update_mibstats() argument
115 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL); in ath9k_hw_update_mibstats()
116 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL); in ath9k_hw_update_mibstats()
117 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL); in ath9k_hw_update_mibstats()
118 stats->rts_good += REG_READ(ah, AR_RTS_OK); in ath9k_hw_update_mibstats()
119 stats->beacons += REG_READ(ah, AR_BEACON_CNT); in ath9k_hw_update_mibstats()
122 static void ath9k_ani_restart(struct ath_hw *ah) in ath9k_ani_restart() argument
125 struct ath_common *common = ath9k_hw_common(ah); in ath9k_ani_restart()
[all …]
Dar9003_phy.c68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar9003_hw_set_channel() argument
75 ath9k_hw_get_channel_centers(ah, chan, &centers); in ar9003_hw_set_channel()
79 if (AR_SREV_9330(ah)) { in ar9003_hw_set_channel()
83 if (ah->is_clk_25mhz) in ar9003_hw_set_channel()
91 } else if (AR_SREV_9485(ah)) { in ar9003_hw_set_channel()
102 } else if (AR_SREV_9340(ah)) { in ar9003_hw_set_channel()
103 if (ah->is_clk_25mhz) { in ar9003_hw_set_channel()
116 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) { in ar9003_hw_set_channel()
137 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel()
140 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, in ar9003_hw_set_channel()
[all …]
Dar9003_mci.c23 static void ar9003_mci_reset_req_wakeup(struct ath_hw *ah) in ar9003_mci_reset_req_wakeup() argument
25 REG_RMW_FIELD(ah, AR_MCI_COMMAND2, in ar9003_mci_reset_req_wakeup()
28 REG_RMW_FIELD(ah, AR_MCI_COMMAND2, in ar9003_mci_reset_req_wakeup()
32 static int ar9003_mci_wait_for_interrupt(struct ath_hw *ah, u32 address, in ar9003_mci_wait_for_interrupt() argument
35 struct ath_common *common = ath9k_hw_common(ah); in ar9003_mci_wait_for_interrupt()
38 if (REG_READ(ah, address) & bit_position) { in ar9003_mci_wait_for_interrupt()
39 REG_WRITE(ah, address, bit_position); in ar9003_mci_wait_for_interrupt()
44 ar9003_mci_reset_req_wakeup(ah); in ar9003_mci_wait_for_interrupt()
49 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_wait_for_interrupt()
52 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_wait_for_interrupt()
[all …]
Dar5008_phy.c58 ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
60 static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array, in ar5008_write_rf_array() argument
65 ENABLE_REGWRITE_BUFFER(ah); in ar5008_write_rf_array()
68 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_rf_array()
72 REGWRITE_BUFFER_FLUSH(ah); in ar5008_write_rf_array()
139 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) in ar5008_hw_force_bias() argument
141 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_force_bias()
146 if (!AR_SREV_5416(ah) || synth_freq >= 3000) in ar5008_hw_force_bias()
149 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); in ar5008_hw_force_bias()
165 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); in ar5008_hw_force_bias()
[all …]
Dbtcoex.c54 void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum) in ath9k_hw_init_btcoex_hw() argument
56 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; in ath9k_hw_init_btcoex_hw()
71 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_init_btcoex_hw()
93 ah->hw_gen_timers.gen_timer_index[idx] = i; in ath9k_hw_init_btcoex_hw()
98 void ath9k_hw_btcoex_init_scheme(struct ath_hw *ah) in ath9k_hw_btcoex_init_scheme() argument
100 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_btcoex_init_scheme()
101 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; in ath9k_hw_btcoex_init_scheme()
111 if (AR_SREV_9462(ah)) { in ath9k_hw_btcoex_init_scheme()
113 } else if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_btcoex_init_scheme()
118 } else if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_btcoex_init_scheme()
[all …]
Dmac.c21 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, in ath9k_hw_set_txq_interrupts() argument
24 ath_dbg(ath9k_hw_common(ah), INTERRUPT, in ath9k_hw_set_txq_interrupts()
26 ah->txok_interrupt_mask, ah->txerr_interrupt_mask, in ath9k_hw_set_txq_interrupts()
27 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, in ath9k_hw_set_txq_interrupts()
28 ah->txurn_interrupt_mask); in ath9k_hw_set_txq_interrupts()
30 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_txq_interrupts()
32 REG_WRITE(ah, AR_IMR_S0, in ath9k_hw_set_txq_interrupts()
33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) in ath9k_hw_set_txq_interrupts()
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); in ath9k_hw_set_txq_interrupts()
35 REG_WRITE(ah, AR_IMR_S1, in ath9k_hw_set_txq_interrupts()
[all …]
Dhtc_drv_gpio.c33 struct ath_hw *ah = priv->ah; in ath_detect_bt_priority() local
35 if (ath9k_hw_gpio_get(ah, ah->btcoex_hw.btpriority_gpio)) in ath_detect_bt_priority()
43 ath_dbg(ath9k_hw_common(ah), BTCOEX, in ath_detect_bt_priority()
48 ath_dbg(ath9k_hw_common(ah), BTCOEX, in ath_detect_bt_priority()
68 struct ath_common *common = ath9k_hw_common(priv->ah); in ath_btcoex_period_work()
84 ath9k_hw_btcoex_bt_stomp(priv->ah, is_btscan ? ATH_BTCOEX_STOMP_ALL : in ath_btcoex_period_work()
87 ath9k_hw_btcoex_enable(priv->ah); in ath_btcoex_period_work()
104 struct ath_hw *ah = priv->ah; in ath_btcoex_duty_cycle_work() local
106 struct ath_common *common = ath9k_hw_common(ah); in ath_btcoex_duty_cycle_work()
112 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE); in ath_btcoex_duty_cycle_work()
[all …]
Dcalib.c47 static struct ath_nf_limits *ath9k_hw_get_nf_limits(struct ath_hw *ah, in ath9k_hw_get_nf_limits() argument
53 limit = &ah->nf_2g; in ath9k_hw_get_nf_limits()
55 limit = &ah->nf_5g; in ath9k_hw_get_nf_limits()
60 static s16 ath9k_hw_get_default_nf(struct ath_hw *ah, in ath9k_hw_get_default_nf() argument
63 return ath9k_hw_get_nf_limits(ah, chan)->nominal; in ath9k_hw_get_default_nf()
66 s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan) in ath9k_hw_getchan_noise() argument
73 ath9k_hw_get_default_nf(ah, chan); in ath9k_hw_getchan_noise()
81 static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah, in ath9k_hw_update_nfcal_hist_buffer() argument
85 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_update_nfcal_hist_buffer()
89 u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask; in ath9k_hw_update_nfcal_hist_buffer()
[all …]
Dar9003_calib.c38 static void ar9003_hw_setup_calibration(struct ath_hw *ah, in ar9003_hw_setup_calibration() argument
41 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_setup_calibration()
50 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_setup_calibration()
53 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9003_hw_setup_calibration()
59 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); in ar9003_hw_setup_calibration()
62 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM, in ar9003_hw_setup_calibration()
64 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM, in ar9003_hw_setup_calibration()
78 static bool ar9003_hw_per_calibration(struct ath_hw *ah, in ar9003_hw_per_calibration() argument
83 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9003_hw_per_calibration()
90 if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) { in ar9003_hw_per_calibration()
[all …]
Dar9002_phy.c66 static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar9002_hw_set_channel() argument
73 ath9k_hw_get_channel_centers(ah, chan, &centers); in ar9002_hw_set_channel()
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
88 if (AR_SREV_9287_11_OR_LATER(ah)) { in ar9002_hw_set_channel()
91 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484, in ar9002_hw_set_channel()
94 REG_WRITE_ARRAY(&ah->iniCckfirNormal, in ar9002_hw_set_channel()
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar9002_hw_set_channel()
101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) { in ar9002_hw_set_channel()
[all …]
/drivers/net/wireless/ath/ath5k/
Dattach.c33 static int ath5k_hw_post(struct ath5k_hw *ah) in ath5k_hw_post() argument
52 init_val = ath5k_hw_reg_read(ah, cur_reg); in ath5k_hw_post()
56 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
57 cur_val = ath5k_hw_reg_read(ah, cur_reg); in ath5k_hw_post()
60 ATH5K_ERR(ah, "POST Failed !!!\n"); in ath5k_hw_post()
66 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
71 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
72 cur_val = ath5k_hw_reg_read(ah, cur_reg); in ath5k_hw_post()
75 ATH5K_ERR(ah, "POST Failed !!!\n"); in ath5k_hw_post()
81 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
[all …]
Dbase.c97 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
193 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) in ath5k_extend_tsf() argument
195 u64 tsf = ath5k_hw_get_tsf64(ah); in ath5k_extend_tsf()
226 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; in ath5k_ioread32() local
227 return ath5k_hw_reg_read(ah, reg_offset); in ath5k_ioread32()
232 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; in ath5k_iowrite32() local
233 ath5k_hw_reg_write(ah, val, reg_offset); in ath5k_iowrite32()
248 struct ath5k_hw *ah = hw->priv; in ath5k_reg_notifier() local
249 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); in ath5k_reg_notifier()
279 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, in ath5k_setup_channels() argument
[all …]
Dreset.c65 ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, in ath5k_hw_register_timeout() argument
72 data = ath5k_hw_reg_read(ah, reg); in ath5k_hw_register_timeout()
99 ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec) in ath5k_hw_htoclock() argument
101 struct ath_common *common = ath5k_hw_common(ah); in ath5k_hw_htoclock()
116 ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock) in ath5k_hw_clocktoh() argument
118 struct ath_common *common = ath5k_hw_common(ah); in ath5k_hw_clocktoh()
130 ath5k_hw_init_core_clock(struct ath5k_hw *ah) in ath5k_hw_init_core_clock() argument
132 struct ieee80211_channel *channel = ah->ah_current_channel; in ath5k_hw_init_core_clock()
133 struct ath_common *common = ath5k_hw_common(ah); in ath5k_hw_init_core_clock()
154 switch (ah->ah_bwmode) { in ath5k_hw_init_core_clock()
[all …]
Dani.c64 ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level) in ath5k_ani_set_noise_immunity_level() argument
84 ATH5K_ERR(ah, "noise immunity level %d out of range", in ath5k_ani_set_noise_immunity_level()
89 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, in ath5k_ani_set_noise_immunity_level()
91 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE, in ath5k_ani_set_noise_immunity_level()
93 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE, in ath5k_ani_set_noise_immunity_level()
95 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG, in ath5k_ani_set_noise_immunity_level()
98 ah->ani_state.noise_imm_level = level; in ath5k_ani_set_noise_immunity_level()
99 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level); in ath5k_ani_set_noise_immunity_level()
109 ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level) in ath5k_ani_set_spur_immunity_level() argument
114 level > ah->ani_state.max_spur_level) { in ath5k_ani_set_spur_immunity_level()
[all …]
Dpcu.c113 ath5k_hw_get_frame_duration(struct ath5k_hw *ah, in ath5k_hw_get_frame_duration() argument
121 if (!ah->ah_bwmode) { in ath5k_hw_get_frame_duration()
122 __le16 raw_dur = ieee80211_generic_frame_duration(ah->hw, in ath5k_hw_get_frame_duration()
138 switch (ah->ah_bwmode) { in ath5k_hw_get_frame_duration()
173 ath5k_hw_get_default_slottime(struct ath5k_hw *ah) in ath5k_hw_get_default_slottime() argument
175 struct ieee80211_channel *channel = ah->ah_current_channel; in ath5k_hw_get_default_slottime()
178 switch (ah->ah_bwmode) { in ath5k_hw_get_default_slottime()
191 if ((channel->hw_value == AR5K_MODE_11B) && !ah->ah_short_slot) in ath5k_hw_get_default_slottime()
204 ath5k_hw_get_default_sifs(struct ath5k_hw *ah) in ath5k_hw_get_default_sifs() argument
206 struct ieee80211_channel *channel = ah->ah_current_channel; in ath5k_hw_get_default_sifs()
[all …]
Dqcu.c61 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue) in ath5k_hw_num_tx_pending() argument
64 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); in ath5k_hw_num_tx_pending()
67 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) in ath5k_hw_num_tx_pending()
71 if (ah->ah_version == AR5K_AR5210) in ath5k_hw_num_tx_pending()
74 pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue)); in ath5k_hw_num_tx_pending()
80 if (!pending && AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue)) in ath5k_hw_num_tx_pending()
92 ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue) in ath5k_hw_release_tx_queue() argument
94 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num)) in ath5k_hw_release_tx_queue()
98 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; in ath5k_hw_release_tx_queue()
100 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue); in ath5k_hw_release_tx_queue()
[all …]
Dphy.c82 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band) in ath5k_hw_radio_revision() argument
93 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
96 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
105 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); in ath5k_hw_radio_revision()
108 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); in ath5k_hw_radio_revision()
110 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_radio_revision()
111 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; in ath5k_hw_radio_revision()
114 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; in ath5k_hw_radio_revision()
120 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
134 ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel) in ath5k_channel_ok() argument
[all …]
Ddma.c46 ath5k_hw_start_rx_dma(struct ath5k_hw *ah) in ath5k_hw_start_rx_dma() argument
48 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR); in ath5k_hw_start_rx_dma()
49 ath5k_hw_reg_read(ah, AR5K_CR); in ath5k_hw_start_rx_dma()
57 ath5k_hw_stop_rx_dma(struct ath5k_hw *ah) in ath5k_hw_stop_rx_dma() argument
61 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR); in ath5k_hw_stop_rx_dma()
67 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0; in ath5k_hw_stop_rx_dma()
72 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, in ath5k_hw_stop_rx_dma()
83 ath5k_hw_get_rxdp(struct ath5k_hw *ah) in ath5k_hw_get_rxdp() argument
85 return ath5k_hw_reg_read(ah, AR5K_RXDP); in ath5k_hw_get_rxdp()
96 ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr) in ath5k_hw_set_rxdp() argument
[all …]
Dmac80211-ops.c58 struct ath5k_hw *ah = hw->priv; in ath5k_tx() local
61 if (WARN_ON(qnum >= ah->ah_capabilities.cap_queues.q_tx_num)) { in ath5k_tx()
66 ath5k_tx_queue(hw, skb, &ah->txqs[qnum]); in ath5k_tx()
73 struct ath5k_hw *ah = hw->priv; in ath5k_add_interface() local
77 mutex_lock(&ah->lock); in ath5k_add_interface()
81 && (ah->num_ap_vifs + ah->num_adhoc_vifs) >= ATH_BCBUF) { in ath5k_add_interface()
91 if (ah->num_adhoc_vifs || in ath5k_add_interface()
92 (ah->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) { in ath5k_add_interface()
93 ATH5K_ERR(ah, "Only one single ad-hoc interface is allowed.\n"); in ath5k_add_interface()
110 ah->nvifs++; in ath5k_add_interface()
[all …]
Drfkill.c39 static inline void ath5k_rfkill_disable(struct ath5k_hw *ah) in ath5k_rfkill_disable() argument
41 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "rfkill disable (gpio:%d polarity:%d)\n", in ath5k_rfkill_disable()
42 ah->rf_kill.gpio, ah->rf_kill.polarity); in ath5k_rfkill_disable()
43 ath5k_hw_set_gpio_output(ah, ah->rf_kill.gpio); in ath5k_rfkill_disable()
44 ath5k_hw_set_gpio(ah, ah->rf_kill.gpio, !ah->rf_kill.polarity); in ath5k_rfkill_disable()
48 static inline void ath5k_rfkill_enable(struct ath5k_hw *ah) in ath5k_rfkill_enable() argument
50 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "rfkill enable (gpio:%d polarity:%d)\n", in ath5k_rfkill_enable()
51 ah->rf_kill.gpio, ah->rf_kill.polarity); in ath5k_rfkill_enable()
52 ath5k_hw_set_gpio_output(ah, ah->rf_kill.gpio); in ath5k_rfkill_enable()
53 ath5k_hw_set_gpio(ah, ah->rf_kill.gpio, ah->rf_kill.polarity); in ath5k_rfkill_enable()
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