Searched refs:cnf (Results 1 – 3 of 3) sorted by relevance
/drivers/isdn/hysdn/ |
D | hysdn_procconf.c | 53 process_line(struct conf_writedata *cnf) in process_line() argument 55 unsigned char *cp = cnf->conf_line; in process_line() 58 if (cnf->card->debug_flags & LOG_CNF_LINE) in process_line() 59 hysdn_addlog(cnf->card, "conf line: %s", cp); in process_line() 70 if (cnf->card->debug_flags & LOG_CNF_MISC) in process_line() 71 hysdn_addlog(cnf->card, "conf channel invalid %d", i); in process_line() 74 cnf->channel = i & 0xFFFF; /* set new channel number */ in process_line() 78 if (cnf->card->debug_flags & LOG_CNF_DATA) in process_line() 79 hysdn_addlog(cnf->card, "conf chan=%d %s", cnf->channel, cp); in process_line() 80 return (hysdn_tx_cfgline(cnf->card, cnf->conf_line + 1, in process_line() [all …]
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/drivers/mfd/ |
D | tmio_core.c | 12 int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base) in tmio_core_mmc_enable() argument 15 sd_config_write16(cnf, shift, CNF_CMD, SDCREN); in tmio_core_mmc_enable() 16 sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe); in tmio_core_mmc_enable() 19 sd_config_write8(cnf, shift, CNF_PWR_CTL_3, 0x01); in tmio_core_mmc_enable() 22 sd_config_write8(cnf, shift, CNF_STOP_CLK_CTL, 0x1f); in tmio_core_mmc_enable() 25 sd_config_write8(cnf, shift, CNF_PWR_CTL_2, 0x00); in tmio_core_mmc_enable() 31 int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base) in tmio_core_mmc_resume() argument 35 sd_config_write16(cnf, shift, CNF_CMD, SDCREN); in tmio_core_mmc_resume() 36 sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe); in tmio_core_mmc_resume() 42 void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state) in tmio_core_mmc_pwr() argument [all …]
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/drivers/gpio/ |
D | gpio-tegra.c | 71 u32 cnf[4]; member 288 tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio)); in tegra_gpio_resume() 311 bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio)); in tegra_gpio_suspend()
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