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Searched refs:csrow (Results 1 – 25 of 26) sorted by relevance

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/drivers/edac/
Dedac_mc.c48 debugf4("\tchannel->csrow = %p\n\n", chan->csrow); in edac_mc_dump_channel()
51 static void edac_mc_dump_csrow(struct csrow_info *csrow) in edac_mc_dump_csrow() argument
53 debugf4("\tcsrow = %p\n", csrow); in edac_mc_dump_csrow()
54 debugf4("\tcsrow->csrow_idx = %d\n", csrow->csrow_idx); in edac_mc_dump_csrow()
55 debugf4("\tcsrow->first_page = 0x%lx\n", csrow->first_page); in edac_mc_dump_csrow()
56 debugf4("\tcsrow->last_page = 0x%lx\n", csrow->last_page); in edac_mc_dump_csrow()
57 debugf4("\tcsrow->page_mask = 0x%lx\n", csrow->page_mask); in edac_mc_dump_csrow()
58 debugf4("\tcsrow->nr_pages = 0x%x\n", csrow->nr_pages); in edac_mc_dump_csrow()
59 debugf4("\tcsrow->nr_channels = %d\n", csrow->nr_channels); in edac_mc_dump_csrow()
60 debugf4("\tcsrow->channels = %p\n", csrow->channels); in edac_mc_dump_csrow()
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Dedac_mc_sysfs.c132 static ssize_t csrow_ue_count_show(struct csrow_info *csrow, char *data, in csrow_ue_count_show() argument
135 return sprintf(data, "%u\n", csrow->ue_count); in csrow_ue_count_show()
138 static ssize_t csrow_ce_count_show(struct csrow_info *csrow, char *data, in csrow_ce_count_show() argument
141 return sprintf(data, "%u\n", csrow->ce_count); in csrow_ce_count_show()
144 static ssize_t csrow_size_show(struct csrow_info *csrow, char *data, in csrow_size_show() argument
147 return sprintf(data, "%u\n", PAGES_TO_MiB(csrow->nr_pages)); in csrow_size_show()
150 static ssize_t csrow_mem_type_show(struct csrow_info *csrow, char *data, in csrow_mem_type_show() argument
153 return sprintf(data, "%s\n", mem_types[csrow->mtype]); in csrow_mem_type_show()
156 static ssize_t csrow_dev_type_show(struct csrow_info *csrow, char *data, in csrow_dev_type_show() argument
159 return sprintf(data, "%s\n", dev_types[csrow->dtype]); in csrow_dev_type_show()
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Dpasemi_edac.c137 struct csrow_info *csrow; in pasemi_edac_init_csrows() local
142 csrow = &mci->csrows[index]; in pasemi_edac_init_csrows()
154 csrow->nr_pages = 128 << (20 - PAGE_SHIFT); in pasemi_edac_init_csrows()
157 csrow->nr_pages = 256 << (20 - PAGE_SHIFT); in pasemi_edac_init_csrows()
161 csrow->nr_pages = 512 << (20 - PAGE_SHIFT); in pasemi_edac_init_csrows()
164 csrow->nr_pages = 1024 << (20 - PAGE_SHIFT); in pasemi_edac_init_csrows()
167 csrow->nr_pages = 2048 << (20 - PAGE_SHIFT); in pasemi_edac_init_csrows()
176 csrow->first_page = last_page_in_mmc; in pasemi_edac_init_csrows()
177 csrow->last_page = csrow->first_page + csrow->nr_pages - 1; in pasemi_edac_init_csrows()
178 last_page_in_mmc += csrow->nr_pages; in pasemi_edac_init_csrows()
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Dtile_edac.c84 struct csrow_info *csrow = &mci->csrows[0]; in tile_edac_init_csrows() local
96 csrow->edac_mode = EDAC_SECDED; in tile_edac_init_csrows()
98 csrow->edac_mode = EDAC_NONE; in tile_edac_init_csrows()
101 csrow->mtype = MEM_DDR2; in tile_edac_init_csrows()
105 csrow->mtype = MEM_DDR3; in tile_edac_init_csrows()
112 csrow->first_page = 0; in tile_edac_init_csrows()
113 csrow->nr_pages = mem_info.mem_size >> PAGE_SHIFT; in tile_edac_init_csrows()
114 csrow->last_page = csrow->first_page + csrow->nr_pages - 1; in tile_edac_init_csrows()
115 csrow->grain = TILE_EDAC_ERROR_GRAIN; in tile_edac_init_csrows()
116 csrow->dtype = DEV_UNKNOWN; in tile_edac_init_csrows()
Damd76x_edac.c188 struct csrow_info *csrow; in amd76x_init_csrows() local
193 csrow = &mci->csrows[index]; in amd76x_init_csrows()
205 csrow->first_page = mba_base >> PAGE_SHIFT; in amd76x_init_csrows()
206 csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT; in amd76x_init_csrows()
207 csrow->last_page = csrow->first_page + csrow->nr_pages - 1; in amd76x_init_csrows()
208 csrow->page_mask = mba_mask >> PAGE_SHIFT; in amd76x_init_csrows()
209 csrow->grain = csrow->nr_pages << PAGE_SHIFT; in amd76x_init_csrows()
210 csrow->mtype = MEM_RDDR; in amd76x_init_csrows()
211 csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN; in amd76x_init_csrows()
212 csrow->edac_mode = edac_mode; in amd76x_init_csrows()
Dcell_edac.c36 struct csrow_info *csrow = &mci->csrows[0]; in cell_edac_count_ce() local
51 edac_mc_handle_ce(mci, csrow->first_page + pfn, offset, in cell_edac_count_ce()
58 struct csrow_info *csrow = &mci->csrows[0]; in cell_edac_count_ue() local
72 edac_mc_handle_ue(mci, csrow->first_page + pfn, offset, 0, ""); in cell_edac_count_ue()
126 struct csrow_info *csrow = &mci->csrows[0]; in cell_edac_init_csrows() local
142 csrow->first_page = r.start >> PAGE_SHIFT; in cell_edac_init_csrows()
143 csrow->nr_pages = resource_size(&r) >> PAGE_SHIFT; in cell_edac_init_csrows()
144 csrow->last_page = csrow->first_page + csrow->nr_pages - 1; in cell_edac_init_csrows()
145 csrow->mtype = MEM_XDR; in cell_edac_init_csrows()
146 csrow->edac_mode = EDAC_SECDED; in cell_edac_init_csrows()
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Damd64_edac.c331 static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, in get_cs_base_and_mask() argument
338 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
339 csmask = pvt->csels[dct].csmasks[csrow]; in get_cs_base_and_mask()
344 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
345 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
379 int csrow; in input_addr_to_csrow() local
384 for_each_chip_select(csrow, 0, pvt) { in input_addr_to_csrow()
385 if (!csrow_enabled(csrow, 0, pvt)) in input_addr_to_csrow()
388 get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); in input_addr_to_csrow()
394 (unsigned long)input_addr, csrow, in input_addr_to_csrow()
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Dr82600_edac.c218 struct csrow_info *csrow; in r82600_init_csrows() local
229 csrow = &mci->csrows[index]; in r82600_init_csrows()
248 csrow->first_page = row_base >> PAGE_SHIFT; in r82600_init_csrows()
249 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; in r82600_init_csrows()
250 csrow->nr_pages = csrow->last_page - csrow->first_page + 1; in r82600_init_csrows()
253 csrow->grain = 1 << 14; in r82600_init_csrows()
254 csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR; in r82600_init_csrows()
256 csrow->dtype = DEV_UNKNOWN; in r82600_init_csrows()
259 csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE; in r82600_init_csrows()
Dcpc925_edac.c331 struct csrow_info *csrow; in cpc925_init_csrows() local
349 csrow = &mci->csrows[index]; in cpc925_init_csrows()
352 csrow->first_page = last_nr_pages; in cpc925_init_csrows()
353 csrow->nr_pages = row_size >> PAGE_SHIFT; in cpc925_init_csrows()
354 csrow->last_page = csrow->first_page + csrow->nr_pages - 1; in cpc925_init_csrows()
355 last_nr_pages = csrow->last_page + 1; in cpc925_init_csrows()
357 csrow->mtype = MEM_RDDR; in cpc925_init_csrows()
358 csrow->edac_mode = EDAC_SECDED; in cpc925_init_csrows()
360 switch (csrow->nr_channels) { in cpc925_init_csrows()
362 csrow->grain = 32; /* four-beat burst of 32 bytes */ in cpc925_init_csrows()
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Di82443bxgx_edac.c191 struct csrow_info *csrow; in i82443bxgx_init_csrows() local
199 csrow = &mci->csrows[index]; in i82443bxgx_init_csrows()
218 csrow->first_page = row_base >> PAGE_SHIFT; in i82443bxgx_init_csrows()
219 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; in i82443bxgx_init_csrows()
220 csrow->nr_pages = csrow->last_page - csrow->first_page + 1; in i82443bxgx_init_csrows()
222 csrow->grain = 1 << 12; in i82443bxgx_init_csrows()
223 csrow->mtype = mtype; in i82443bxgx_init_csrows()
225 csrow->dtype = DEV_UNKNOWN; in i82443bxgx_init_csrows()
227 csrow->edac_mode = edac_mode; in i82443bxgx_init_csrows()
Di5400_edac.c868 static int determine_mtr(struct i5400_pvt *pvt, int csrow, int channel) in determine_mtr() argument
876 n = csrow; in determine_mtr()
880 csrow); in determine_mtr()
916 static void handle_channel(struct i5400_pvt *pvt, int csrow, int channel, in handle_channel() argument
923 mtr = determine_mtr(pvt, csrow, channel); in handle_channel()
928 if (amb_present_reg & (1 << csrow)) { in handle_channel()
957 int csrow, max_csrows; in calculate_dimm_size() local
977 for (csrow = max_csrows - 1; csrow >= 0; csrow--) { in calculate_dimm_size()
981 if (csrow & 0x1) { in calculate_dimm_size()
990 n = snprintf(p, space, "csrow %2d ", csrow); in calculate_dimm_size()
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Di82860_edac.c142 struct csrow_info *csrow; in i82860_init_csrows() local
155 csrow = &mci->csrows[index]; in i82860_init_csrows()
165 csrow->first_page = last_cumul_size; in i82860_init_csrows()
166 csrow->last_page = cumul_size - 1; in i82860_init_csrows()
167 csrow->nr_pages = cumul_size - last_cumul_size; in i82860_init_csrows()
169 csrow->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */ in i82860_init_csrows()
170 csrow->mtype = MEM_RMBS; in i82860_init_csrows()
171 csrow->dtype = DEV_UNKNOWN; in i82860_init_csrows()
172 csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE; in i82860_init_csrows()
Di5000_edac.c959 static int determine_mtr(struct i5000_pvt *pvt, int csrow, int channel) in determine_mtr() argument
964 mtr = pvt->b0_mtr[csrow >> 1]; in determine_mtr()
966 mtr = pvt->b1_mtr[csrow >> 1]; in determine_mtr()
991 static void handle_channel(struct i5000_pvt *pvt, int csrow, int channel, in handle_channel() argument
998 mtr = determine_mtr(pvt, csrow, channel); in handle_channel()
1003 if (amb_present_reg & (1 << (csrow >> 1))) { in handle_channel()
1007 ((csrow & 0x1) == 0x1))) { in handle_channel()
1035 int csrow, max_csrows; in calculate_dimm_size() local
1059 for (csrow = max_csrows - 1; csrow >= 0; csrow--) { in calculate_dimm_size()
1063 if (csrow & 0x1) { in calculate_dimm_size()
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Di82975x_edac.c370 struct csrow_info *csrow; in i82975x_init_csrows() local
388 csrow = &mci->csrows[index]; in i82975x_init_csrows()
398 if (csrow->nr_channels > 1) in i82975x_init_csrows()
409 for (chan = 0; chan < csrow->nr_channels; chan++) in i82975x_init_csrows()
410 strncpy(csrow->channels[chan].label, in i82975x_init_csrows()
417 csrow->first_page = last_cumul_size; in i82975x_init_csrows()
418 csrow->last_page = cumul_size - 1; in i82975x_init_csrows()
419 csrow->nr_pages = cumul_size - last_cumul_size; in i82975x_init_csrows()
421 csrow->grain = 1 << 7; /* 128Byte cache-line resolution */ in i82975x_init_csrows()
422 csrow->mtype = MEM_DDR2; /* I82975x supports only DDR2 */ in i82975x_init_csrows()
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Di3000_edac.c381 struct csrow_info *csrow = &mci->csrows[i]; in i3000_probe1() local
390 csrow->mtype = MEM_EMPTY; in i3000_probe1()
394 csrow->first_page = last_cumul_size; in i3000_probe1()
395 csrow->last_page = cumul_size - 1; in i3000_probe1()
396 csrow->nr_pages = cumul_size - last_cumul_size; in i3000_probe1()
398 csrow->grain = I3000_DEAP_GRAIN; in i3000_probe1()
399 csrow->mtype = MEM_DDR2; in i3000_probe1()
400 csrow->dtype = DEV_UNKNOWN; in i3000_probe1()
401 csrow->edac_mode = EDAC_UNKNOWN; in i3000_probe1()
De7xxx_edac.c354 struct csrow_info *csrow; in e7xxx_init_csrows() local
370 csrow = &mci->csrows[index]; in e7xxx_init_csrows()
380 csrow->first_page = last_cumul_size; in e7xxx_init_csrows()
381 csrow->last_page = cumul_size - 1; in e7xxx_init_csrows()
382 csrow->nr_pages = cumul_size - last_cumul_size; in e7xxx_init_csrows()
384 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */ in e7xxx_init_csrows()
385 csrow->mtype = MEM_RDDR; /* only one type supported */ in e7xxx_init_csrows()
386 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8; in e7xxx_init_csrows()
394 csrow->edac_mode = EDAC_S4ECD4ED; in e7xxx_init_csrows()
397 csrow->edac_mode = EDAC_SECDED; in e7xxx_init_csrows()
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Dx38_edac.c369 struct csrow_info *csrow = &mci->csrows[i]; in x38_probe1() local
376 csrow->mtype = MEM_EMPTY; in x38_probe1()
380 csrow->first_page = last_page + 1; in x38_probe1()
382 csrow->last_page = last_page; in x38_probe1()
383 csrow->nr_pages = nr_pages; in x38_probe1()
385 csrow->grain = nr_pages << PAGE_SHIFT; in x38_probe1()
386 csrow->mtype = MEM_DDR2; in x38_probe1()
387 csrow->dtype = DEV_UNKNOWN; in x38_probe1()
388 csrow->edac_mode = EDAC_UNKNOWN; in x38_probe1()
Di82875p_edac.c344 struct csrow_info *csrow; in i82875p_init_csrows() local
361 csrow = &mci->csrows[index]; in i82875p_init_csrows()
370 csrow->first_page = last_cumul_size; in i82875p_init_csrows()
371 csrow->last_page = cumul_size - 1; in i82875p_init_csrows()
372 csrow->nr_pages = cumul_size - last_cumul_size; in i82875p_init_csrows()
374 csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */ in i82875p_init_csrows()
375 csrow->mtype = MEM_DDR; in i82875p_init_csrows()
376 csrow->dtype = DEV_UNKNOWN; in i82875p_init_csrows()
377 csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE; in i82875p_init_csrows()
Di3200_edac.c372 struct csrow_info *csrow = &mci->csrows[i]; in i3200_probe1() local
379 csrow->mtype = MEM_EMPTY; in i3200_probe1()
383 csrow->first_page = last_page + 1; in i3200_probe1()
385 csrow->last_page = last_page; in i3200_probe1()
386 csrow->nr_pages = nr_pages; in i3200_probe1()
388 csrow->grain = nr_pages << PAGE_SHIFT; in i3200_probe1()
389 csrow->mtype = MEM_DDR2; in i3200_probe1()
390 csrow->dtype = DEV_UNKNOWN; in i3200_probe1()
391 csrow->edac_mode = EDAC_UNKNOWN; in i3200_probe1()
Di5100_edac.c398 static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow) in i5100_csrow_to_rank() argument
402 return csrow % priv->ranksperchan; in i5100_csrow_to_rank()
406 static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow) in i5100_csrow_to_chan() argument
410 return csrow / priv->ranksperchan; in i5100_csrow_to_chan()
430 const int csrow = i5100_rank_to_csrow(mci, chan, rank); in i5100_handle_ce() local
436 csrow, mci->csrows[csrow].channels[0].label, msg); in i5100_handle_ce()
439 mci->csrows[csrow].ce_count++; in i5100_handle_ce()
440 mci->csrows[csrow].channels[0].ce_count++; in i5100_handle_ce()
452 const int csrow = i5100_rank_to_csrow(mci, chan, rank); in i5100_handle_ue() local
458 csrow, mci->csrows[csrow].channels[0].label, msg); in i5100_handle_ue()
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Dmv64x60_edac.c658 struct csrow_info *csrow; in mv64x60_init_csrows() local
666 csrow = &mci->csrows[0]; in mv64x60_init_csrows()
667 csrow->first_page = 0; in mv64x60_init_csrows()
668 csrow->nr_pages = pdata->total_mem >> PAGE_SHIFT; in mv64x60_init_csrows()
669 csrow->last_page = csrow->first_page + csrow->nr_pages - 1; in mv64x60_init_csrows()
670 csrow->grain = 8; in mv64x60_init_csrows()
672 csrow->mtype = (ctl & MV64X60_SDRAM_REGISTERED) ? MEM_RDDR : MEM_DDR; in mv64x60_init_csrows()
677 csrow->dtype = DEV_X32; in mv64x60_init_csrows()
680 csrow->dtype = DEV_X16; in mv64x60_init_csrows()
683 csrow->dtype = DEV_X4; in mv64x60_init_csrows()
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Dmpc85xx_edac.c777 struct csrow_info *csrow; in mpc85xx_mc_check() local
816 csrow = &mci->csrows[row_index]; in mpc85xx_mc_check()
817 if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page)) in mpc85xx_mc_check()
885 struct csrow_info *csrow; in mpc85xx_init_csrows() local
931 csrow = &mci->csrows[index]; in mpc85xx_init_csrows()
945 csrow->first_page = start; in mpc85xx_init_csrows()
946 csrow->last_page = end; in mpc85xx_init_csrows()
947 csrow->nr_pages = end + 1 - start; in mpc85xx_init_csrows()
948 csrow->grain = 8; in mpc85xx_init_csrows()
949 csrow->mtype = mtype; in mpc85xx_init_csrows()
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De752x_edac.c1041 struct csrow_info *csrow; in e752x_init_csrows() local
1068 csrow = &mci->csrows[remap_csrow_index(mci, index)]; in e752x_init_csrows()
1079 csrow->first_page = last_cumul_size; in e752x_init_csrows()
1080 csrow->last_page = cumul_size - 1; in e752x_init_csrows()
1081 csrow->nr_pages = cumul_size - last_cumul_size; in e752x_init_csrows()
1083 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */ in e752x_init_csrows()
1084 csrow->mtype = MEM_RDDR; /* only one type supported */ in e752x_init_csrows()
1085 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8; in e752x_init_csrows()
1093 csrow->edac_mode = EDAC_S4ECD4ED; in e752x_init_csrows()
1096 csrow->edac_mode = EDAC_SECDED; in e752x_init_csrows()
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Dsb_edac.c559 int csrow = 0; in get_dimm_config() local
637 csr = &mci->csrows[csrow]; in get_dimm_config()
644 csr->csrow_idx = csrow; in get_dimm_config()
653 pvt->csrow_map[i][j] = csrow; in get_dimm_config()
659 csrow++; in get_dimm_config()
1424 int csrow, rc, dimm; in sbridge_mce_output_error() local
1489 csrow = pvt->csrow_map[first_channel][dimm]; in sbridge_mce_output_error()
1523 edac_mc_handle_fbd_ue(mci, csrow, 0, 0, msg); in sbridge_mce_output_error()
1525 edac_mc_handle_fbd_ce(mci, csrow, 0, msg); in sbridge_mce_output_error()
Di7core_edac.c601 int csrow = 0; in get_dimm_config() local
717 csr = &mci->csrows[csrow]; in get_dimm_config()
725 csr->csrow_idx = csrow; in get_dimm_config()
731 pvt->csrow_map[i][j] = csrow; in get_dimm_config()
754 csrow++; in get_dimm_config()
1758 int csrow; in i7core_mce_output_error() local
1828 csrow = pvt->csrow_map[channel][dimm]; in i7core_mce_output_error()
1832 edac_mc_handle_fbd_ue(mci, csrow, 0, in i7core_mce_output_error()
1835 edac_mc_handle_fbd_ce(mci, csrow, in i7core_mce_output_error()

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