Searched refs:idx_value (Results 1 – 7 of 7) sorted by relevance
155 u32 idx_value; in r200_packet0_check() local159 idx_value = radeon_get_ib_value(p, idx); in r200_packet0_check()187 track->zb.offset = idx_value; in r200_packet0_check()189 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()200 track->cb[0].offset = idx_value; in r200_packet0_check()202 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()224 tmp = idx_value & ~(0x7 << 2); in r200_packet0_check()228 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()271 track->textures[i].cube_info[face - 1].offset = idx_value; in r200_packet0_check()272 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()[all …]
628 u32 idx_value; in r300_packet0_check() local632 idx_value = radeon_get_ib_value(p, idx); in r300_packet0_check()664 track->cb[i].offset = idx_value; in r300_packet0_check()666 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r300_packet0_check()677 track->zb.offset = idx_value; in r300_packet0_check()679 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r300_packet0_check()707 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ in r300_packet0_check()708 ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset); in r300_packet0_check()717 tmp = idx_value + ((u32)reloc->lobj.gpu_offset); in r300_packet0_check()727 track->vap_vf_cntl = idx_value; in r300_packet0_check()[all …]
157 u32 idx_value; in r100_packet3_load_vbpntr() local177 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()180 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()192 track->arrays[i + 1].esize = idx_value >> 24; in r100_packet3_load_vbpntr()203 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()206 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()1530 u32 idx_value; in r100_packet0_check() local1535 idx_value = radeon_get_ib_value(p, idx); in r100_packet0_check()1564 track->zb.offset = idx_value; in r100_packet0_check()1566 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r100_packet0_check()[all …]
1937 u32 idx_value; in evergreen_packet3_check() local1942 idx_value = radeon_get_ib_value(p, idx); in evergreen_packet3_check()1975 (idx_value & 0xfffffff0) + in evergreen_packet3_check()2021 idx_value + in evergreen_packet3_check()2048 idx_value + in evergreen_packet3_check()2165 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); in evergreen_packet3_check()2178 if (idx_value & 0x10) { in evergreen_packet3_check()2277 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in evergreen_packet3_check()2293 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START; in evergreen_packet3_check()2313 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START; in evergreen_packet3_check()[all …]
1714 u32 idx_value; in r600_packet3_check() local1719 idx_value = radeon_get_ib_value(p, idx); in r600_packet3_check()1752 (idx_value & 0xfffffff0) + in r600_packet3_check()1793 idx_value + in r600_packet3_check()1835 if (idx_value & 0x10) { in r600_packet3_check()1912 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; in r600_packet3_check()1928 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; in r600_packet3_check()1948 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; in r600_packet3_check()2028 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET; in r600_packet3_check()2039 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET; in r600_packet3_check()[all …]
43 u32 idx_value = 0; in radeon_get_ib_value() local60 idx_value = ibc->kpage[new_page][pg_offset/4]; in radeon_get_ib_value()61 return idx_value; in radeon_get_ib_value()
2670 u32 idx_value = ib[idx]; in si_vm_packet3_gfx_check() local2721 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()2728 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()2730 if (idx_value & 0x10000) { in si_vm_packet3_gfx_check()2743 if (idx_value & 0x100) { in si_vm_packet3_gfx_check()2750 if (idx_value & 0x2) { in si_vm_packet3_gfx_check()2757 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in si_vm_packet3_gfx_check()2782 u32 idx_value = ib[idx]; in si_vm_packet3_compute_check() local2818 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_compute_check()2825 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_compute_check()[all …]