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Searched refs:radeon_crtc (Results 1 – 20 of 20) sorted by relevance

/drivers/gpu/drm/radeon/
Dradeon_cursor.c36 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_lock_cursor() local
40 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); in radeon_lock_cursor()
45 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
47 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); in radeon_lock_cursor()
52 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
54 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); in radeon_lock_cursor()
59 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
65 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_hide_cursor() local
69 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); in radeon_hide_cursor()
72 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); in radeon_hide_cursor()
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Dradeon_display.c38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in avivo_crtc_load_lut() local
43 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in avivo_crtc_load_lut()
44 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
46 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
47 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
50 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
51 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
54 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); in avivo_crtc_load_lut()
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Datombios_crtc.c40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_overscan_setup() local
47 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
49 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_scaler_setup() local
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) in atombios_scaler_setup()
109 args.ucScaler = radeon_crtc->crtc_id; in atombios_scaler_setup()
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Dradeon_legacy_crtc.c38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_overscan_setup() local
40 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
41 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
42 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
50 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_legacy_rmx_mode_set() local
62 struct drm_display_mode *native_mode = &radeon_crtc->native_mode; in radeon_legacy_rmx_mode_set()
125 switch (radeon_crtc->rmx_type) { in radeon_legacy_rmx_mode_set()
300 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_crtc_dpms() local
305 if (radeon_crtc->crtc_id) in radeon_crtc_dpms()
317 radeon_crtc->enabled = true; in radeon_crtc_dpms()
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Drs600.c51 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc]; in avivo_wait_for_vblank() local
54 if (RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset) & AVIVO_CRTC_EN) { in avivo_wait_for_vblank()
56 if (!(RREG32(AVIVO_D1CRTC_STATUS + radeon_crtc->crtc_offset) & AVIVO_D1CRTC_V_BLANK)) in avivo_wait_for_vblank()
61 if (RREG32(AVIVO_D1CRTC_STATUS + radeon_crtc->crtc_offset) & AVIVO_D1CRTC_V_BLANK) in avivo_wait_for_vblank()
82 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip() local
83 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
88 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
91 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
93 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
98 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
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Dradeon_legacy_encoders.c182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_lvds_mode_set() local
220 if (radeon_crtc->crtc_id == 0) { in radeon_legacy_lvds_mode_set()
241 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_lvds_mode_set()
243 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_lvds_mode_set()
559 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_primary_dac_mode_set() local
565 if (radeon_crtc->crtc_id == 0) { in radeon_legacy_primary_dac_mode_set()
605 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_primary_dac_mode_set()
607 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_primary_dac_mode_set()
754 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_tmds_int_mode_set() local
821 if (radeon_crtc->crtc_id == 0) { in radeon_legacy_tmds_int_mode_set()
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Dradeon_legacy_tv.c239 struct radeon_crtc *radeon_crtc; in radeon_legacy_tv_get_std_mode() local
244 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); in radeon_legacy_tv_get_std_mode()
245 if (radeon_crtc->crtc_id == 1) in radeon_legacy_tv_get_std_mode()
427 struct radeon_crtc *radeon_crtc; in radeon_legacy_tv_init_restarts() local
436 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); in radeon_legacy_tv_init_restarts()
437 if (radeon_crtc->crtc_id == 1) in radeon_legacy_tv_init_restarts()
540 struct radeon_crtc *radeon_crtc; in radeon_legacy_tv_mode_set() local
557 radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_tv_mode_set()
603 if (radeon_crtc->crtc_id == 1) in radeon_legacy_tv_mode_set()
606 if (radeon_crtc->rmx_type != RMX_OFF) in radeon_legacy_tv_mode_set()
Dradeon_mode.h45 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
227 struct radeon_crtc *crtcs[6];
263 struct radeon_crtc { struct
662 struct radeon_crtc *radeon_crtc);
664 struct radeon_crtc *radeon_crtc);
679 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
Datombios_encoders.c765 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in atombios_dig_transmitter_setup() local
766 pll_id = radeon_crtc->pll_id; in atombios_dig_transmitter_setup()
1269 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in atombios_yuv_setup() local
1285 (radeon_crtc->crtc_id << 18))); in atombios_yuv_setup()
1287 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); in atombios_yuv_setup()
1293 args.ucCRTC = radeon_crtc->crtc_id; in atombios_yuv_setup()
1596 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in atombios_set_encoder_crtc_source() local
1613 args.v1.ucCRTC = radeon_crtc->crtc_id; in atombios_set_encoder_crtc_source()
1616 args.v1.ucCRTC = radeon_crtc->crtc_id; in atombios_set_encoder_crtc_source()
1618 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; in atombios_set_encoder_crtc_source()
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Devergreen.c147 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip() local
148 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset); in evergreen_page_flip()
153 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in evergreen_page_flip()
156 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in evergreen_page_flip()
158 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in evergreen_page_flip()
161 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in evergreen_page_flip()
163 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in evergreen_page_flip()
168 …if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDI… in evergreen_page_flip()
176 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in evergreen_page_flip()
179 …return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PE… in evergreen_page_flip()
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Dr600_audio.c242 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in r600_audio_set_clock() local
269 WREG32(0x5ac, radeon_crtc->crtc_id); in r600_audio_set_clock()
Drv770.c48 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rv770_page_flip() local
49 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rv770_page_flip()
54 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
57 if (radeon_crtc->crtc_id) { in rv770_page_flip()
64 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
66 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
71 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rv770_page_flip()
79 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
82 …return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDIN… in rv770_page_flip()
Dsi.c410 struct radeon_crtc *radeon_crtc, in dce6_line_buffer_adjust() argument
415 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce6_line_buffer_adjust()
429 if (radeon_crtc->base.enabled && mode) { in dce6_line_buffer_adjust()
442 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, in dce6_line_buffer_adjust()
454 if (radeon_crtc->base.enabled && mode) { in dce6_line_buffer_adjust()
750 struct radeon_crtc *radeon_crtc, in dce6_program_watermarks() argument
753 struct drm_display_mode *mode = &radeon_crtc->base.mode; in dce6_program_watermarks()
764 if (radeon_crtc->base.enabled && num_heads && mode) { in dce6_program_watermarks()
779 wm.vsc = radeon_crtc->vsc; in dce6_program_watermarks()
781 if (radeon_crtc->rmx_type != RMX_OFF) in dce6_program_watermarks()
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Dr100.c70 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc]; in r100_wait_for_vblank() local
73 if (radeon_crtc->crtc_id == 0) { in r100_wait_for_vblank()
226 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip() local
232 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
236 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
244 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
247 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET; in r100_page_flip()
466 struct radeon_crtc *radeon_crtc; in r100_pm_prepare() local
471 radeon_crtc = to_radeon_crtc(crtc); in r100_pm_prepare()
472 if (radeon_crtc->enabled) { in r100_pm_prepare()
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Dradeon_pm.c708 struct radeon_crtc *radeon_crtc; in radeon_pm_compute_clocks() local
719 radeon_crtc = to_radeon_crtc(crtc); in radeon_pm_compute_clocks()
720 if (radeon_crtc->enabled) { in radeon_pm_compute_clocks()
721 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); in radeon_pm_compute_clocks()
Dradeon_kms.c159 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_info_ioctl() local
160 value = radeon_crtc->crtc_id; in radeon_info_ioctl()
Devergreen_cs.c1092 struct radeon_crtc *radeon_crtc; in evergreen_cs_packet_parse_vline() local
1152 radeon_crtc = to_radeon_crtc(crtc); in evergreen_cs_packet_parse_vline()
1153 crtc_id = radeon_crtc->crtc_id; in evergreen_cs_packet_parse_vline()
1168 header |= (EVERGREEN_VLINE_START_END + radeon_crtc->crtc_offset) >> 2; in evergreen_cs_packet_parse_vline()
1170 ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2; in evergreen_cs_packet_parse_vline()
Dr600_cs.c957 struct radeon_crtc *radeon_crtc; in r600_cs_packet_parse_vline() local
1018 radeon_crtc = to_radeon_crtc(crtc); in r600_cs_packet_parse_vline()
1019 crtc_id = radeon_crtc->crtc_id; in r600_cs_packet_parse_vline()
Drv515.c560 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) in atom_rv515_force_tv_scaler()
804 struct radeon_crtc *crtc, in rv515_crtc_bandwidth_compute()
Drs690.c228 struct radeon_crtc *crtc, in rs690_crtc_bandwidth_compute()