/drivers/net/wireless/rtlwifi/rtl8192ce/ |
D | rf.c | 358 u16 regoffset; in _rtl92c_write_ofdm_power_reg() local 373 regoffset = regoffset_a[index]; in _rtl92c_write_ofdm_power_reg() 375 regoffset = regoffset_b[index]; in _rtl92c_write_ofdm_power_reg() 376 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal); in _rtl92c_write_ofdm_power_reg() 379 "Set 0x%x = %08x\n", regoffset, writeVal); in _rtl92c_write_ofdm_power_reg() 382 (regoffset == RTXAGC_A_MCS15_MCS12 || in _rtl92c_write_ofdm_power_reg() 383 regoffset == RTXAGC_B_MCS15_MCS12)) || in _rtl92c_write_ofdm_power_reg() 385 (regoffset == RTXAGC_A_MCS07_MCS04 || in _rtl92c_write_ofdm_power_reg() 386 regoffset == RTXAGC_B_MCS07_MCS04))) { in _rtl92c_write_ofdm_power_reg() 389 if (regoffset == RTXAGC_A_MCS15_MCS12 || in _rtl92c_write_ofdm_power_reg() [all …]
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/drivers/net/wireless/rtlwifi/rtl8192cu/ |
D | rf.c | 349 u16 regoffset; in _rtl92c_write_ofdm_power_reg() local 362 regoffset = regoffset_a[index]; in _rtl92c_write_ofdm_power_reg() 364 regoffset = regoffset_b[index]; in _rtl92c_write_ofdm_power_reg() 365 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal); in _rtl92c_write_ofdm_power_reg() 367 "Set 0x%x = %08x\n", regoffset, writeVal); in _rtl92c_write_ofdm_power_reg() 369 (regoffset == RTXAGC_A_MCS15_MCS12 || in _rtl92c_write_ofdm_power_reg() 370 regoffset == RTXAGC_B_MCS15_MCS12)) || in _rtl92c_write_ofdm_power_reg() 372 (regoffset == RTXAGC_A_MCS07_MCS04 || in _rtl92c_write_ofdm_power_reg() 373 regoffset == RTXAGC_B_MCS07_MCS04))) { in _rtl92c_write_ofdm_power_reg() 375 if (regoffset == RTXAGC_A_MCS15_MCS12 || in _rtl92c_write_ofdm_power_reg() [all …]
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/drivers/net/wireless/rtlwifi/rtl8192de/ |
D | rf.c | 349 u16 regoffset; in _rtl92d_write_ofdm_power_reg() local 362 regoffset = regoffset_a[index]; in _rtl92d_write_ofdm_power_reg() 364 regoffset = regoffset_b[index]; in _rtl92d_write_ofdm_power_reg() 365 rtl_set_bbreg(hw, regoffset, BMASKDWORD, writeval); in _rtl92d_write_ofdm_power_reg() 367 "Set 0x%x = %08x\n", regoffset, writeval); in _rtl92d_write_ofdm_power_reg() 369 (regoffset == RTXAGC_A_MCS15_MCS12 || in _rtl92d_write_ofdm_power_reg() 370 regoffset == RTXAGC_B_MCS15_MCS12)) || in _rtl92d_write_ofdm_power_reg() 372 (regoffset == RTXAGC_A_MCS07_MCS04 || in _rtl92d_write_ofdm_power_reg() 373 regoffset == RTXAGC_B_MCS07_MCS04))) { in _rtl92d_write_ofdm_power_reg() 375 if (regoffset == RTXAGC_A_MCS15_MCS12 || in _rtl92d_write_ofdm_power_reg() [all …]
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/drivers/gpio/ |
D | gpio-tc3589x.c | 117 int regoffset = offset / 8; in tc3589x_gpio_irq_set_type() local 121 tc3589x_gpio->regs[REG_IBE][regoffset] |= mask; in tc3589x_gpio_irq_set_type() 125 tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask; in tc3589x_gpio_irq_set_type() 128 tc3589x_gpio->regs[REG_IS][regoffset] |= mask; in tc3589x_gpio_irq_set_type() 130 tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask; in tc3589x_gpio_irq_set_type() 133 tc3589x_gpio->regs[REG_IEV][regoffset] |= mask; in tc3589x_gpio_irq_set_type() 135 tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask; in tc3589x_gpio_irq_set_type() 179 int regoffset = offset / 8; in tc3589x_gpio_irq_mask() local 182 tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask; in tc3589x_gpio_irq_mask() 189 int regoffset = offset / 8; in tc3589x_gpio_irq_unmask() local [all …]
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D | gpio-stmpe.c | 136 int regoffset = offset / 8; in stmpe_gpio_irq_set_type() local 147 stmpe_gpio->regs[REG_RE][regoffset] |= mask; in stmpe_gpio_irq_set_type() 149 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; in stmpe_gpio_irq_set_type() 152 stmpe_gpio->regs[REG_FE][regoffset] |= mask; in stmpe_gpio_irq_set_type() 154 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; in stmpe_gpio_irq_set_type() 203 int regoffset = offset / 8; in stmpe_gpio_irq_mask() local 206 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; in stmpe_gpio_irq_mask() 213 int regoffset = offset / 8; in stmpe_gpio_irq_unmask() local 216 stmpe_gpio->regs[REG_IE][regoffset] |= mask; in stmpe_gpio_irq_unmask()
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/drivers/gpu/drm/nouveau/ |
D | nv04_dac.c | 225 uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder); in nv17_dac_sample_load() local 243 saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); in nv17_dac_sample_load() 244 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, in nv17_dac_sample_load() 250 if (regoffset == 0x68) { in nv17_dac_sample_load() 263 saved_routput = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset); in nv17_dac_sample_load() 280 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, routput); in nv17_dac_sample_load() 283 temp = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset); in nv17_dac_sample_load() 284 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, temp | 1); in nv17_dac_sample_load() 293 sample = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); in nv17_dac_sample_load() 295 sample &= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); in nv17_dac_sample_load() [all …]
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D | nv17_tv.c | 41 uint32_t testval, regoffset = nv04_dac_output_offset(encoder); in nv42_tv_sample_load() local 52 dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset); in nv42_tv_sample_load() 62 test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); in nv42_tv_sample_load() 81 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0); in nv42_tv_sample_load() 83 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, in nv42_tv_sample_load() 86 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, in nv42_tv_sample_load() 95 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset) in nv42_tv_sample_load() 101 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset) in nv42_tv_sample_load() 108 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk); in nv42_tv_sample_load() 109 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl); in nv42_tv_sample_load()
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/drivers/mfd/ |
D | stmpe.c | 267 int regoffset = numregs - (pin / afperreg) - 1; in stmpe_set_altfunc() local 270 regs[regoffset] &= ~(mask << pos); in stmpe_set_altfunc() 271 regs[regoffset] |= af << pos; in stmpe_set_altfunc() 832 int regoffset = offset / 8; in stmpe_irq_mask() local 835 stmpe->ier[regoffset] &= ~mask; in stmpe_irq_mask() 842 int regoffset = offset / 8; in stmpe_irq_unmask() local 845 stmpe->ier[regoffset] |= mask; in stmpe_irq_unmask()
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D | ab8500-core.c | 336 int regoffset = ab8500->irq_reg_offset[i]; in ab8500_irq() local 344 if (regoffset == 11 && is_ab8500_1p1_or_earlier(ab8500)) in ab8500_irq() 348 AB8500_IT_LATCH1_REG + regoffset, &value); in ab8500_irq()
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/drivers/net/wireless/rtlwifi/rtl8192se/ |
D | rf.c | 322 u16 regoffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; in _rtl92s_write_ofdm_powerreg() local 370 rtl_set_bbreg(hw, regoffset[index], 0x7f7f7f7f, writeval); in _rtl92s_write_ofdm_powerreg()
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/drivers/video/ |
D | cirrusfb.c | 285 u32 regoffset; /* Offset of registers in first Zorro device */ member 315 .regoffset = 0x00600000, 322 .regoffset = 0x10000, 2258 regbase = zorro_resource_start(z) + zcl->regoffset; in cirrusfb_zorro_register()
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