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Searched refs:vmw_read (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/vmwgfx/
Dvmwgfx_drv.c356 vmw_read(dev_priv, SVGA_REG_ENABLE) & in vmw_3d_resource_inc()
384 vmw_read(dev_priv, SVGA_REG_ENABLE) | in vmw_3d_resource_dec()
409 width = vmw_read(dev_priv, SVGA_REG_WIDTH); in vmw_get_initial_size()
410 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); in vmw_get_initial_size()
472 svga_id = vmw_read(dev_priv, SVGA_REG_ID); in vmw_driver_load()
480 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); in vmw_driver_load()
482 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); in vmw_driver_load()
483 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); in vmw_driver_load()
484 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); in vmw_driver_load()
485 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); in vmw_driver_load()
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Dvmwgfx_fifo.c102 DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH)); in vmw_fifo_init()
103 DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT)); in vmw_fifo_init()
104 DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL)); in vmw_fifo_init()
107 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_fifo_init()
108 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); in vmw_fifo_init()
109 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); in vmw_fifo_init()
114 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS); in vmw_fifo_init()
166 while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0) in vmw_fifo_release()
Dvmwgfx_kms.c1516 if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) { in vmw_kms_write_svga()
1518 depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH)); in vmw_kms_write_svga()
1530 vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH); in vmw_kms_save_vga()
1531 vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT); in vmw_kms_save_vga()
1532 vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL); in vmw_kms_save_vga()
1535 vmw_read(vmw_priv, SVGA_REG_PITCHLOCK); in vmw_kms_save_vga()
1543 vmw_priv->num_displays = vmw_read(vmw_priv, in vmw_kms_save_vga()
1552 save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY); in vmw_kms_save_vga()
1553 save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X); in vmw_kms_save_vga()
1554 save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y); in vmw_kms_save_vga()
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Dvmwgfx_fb.c186 WARN_ON(vmw_read(vmw_priv, SVGA_REG_FB_OFFSET) != 0); in vmw_fb_set_par()
429 fb_offset = vmw_read(vmw_priv, SVGA_REG_FB_OFFSET); in vmw_fb_init()
Dvmwgfx_irq.c68 busy = vmw_read(dev_priv, SVGA_REG_BUSY); in vmw_fifo_idle()
Dvmwgfx_drv.h358 static inline uint32_t vmw_read(struct vmw_private *dev_priv, in vmw_read() function