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Searched refs:vram_start (Results 1 – 24 of 24) sorted by relevance

/drivers/gpu/drm/radeon/
Dradeon_test.c78 void **vram_start, **vram_end; in radeon_test_moves() local
136 vram_start = vram_map, vram_end = vram_map + size; in radeon_test_moves()
137 vram_start < vram_end; in radeon_test_moves()
138 gtt_start++, vram_start++) { in radeon_test_moves()
139 if (*vram_start != gtt_start) { in radeon_test_moves()
143 i, *vram_start, gtt_start, in radeon_test_moves()
148 (vram_addr - rdev->mc.vram_start + in radeon_test_moves()
153 *vram_start = vram_start; in radeon_test_moves()
185 vram_start = vram_map, vram_end = vram_map + size; in radeon_test_moves()
187 gtt_start++, vram_start++) { in radeon_test_moves()
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Dradeon_device.c298 mc->vram_start = base; in radeon_vram_location()
304 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in radeon_vram_location()
305 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { in radeon_vram_location()
310 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in radeon_vram_location()
314 mc->mc_vram_size >> 20, mc->vram_start, in radeon_vram_location()
335 size_bf = mc->vram_start & ~mc->gtt_base_align; in radeon_gtt_location()
341 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; in radeon_gtt_location()
Drv770.c266 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in rv770_mc_program()
269 rdev->mc.vram_start >> 12); in rv770_mc_program()
281 rdev->mc.vram_start >> 12); in rv770_mc_program()
287 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in rv770_mc_program()
289 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in rv770_mc_program()
988 mc->vram_start = mc->gtt_start - mc->mc_vram_size; in r700_vram_gtt_location()
995 mc->vram_start = mc->gtt_end + 1; in r700_vram_gtt_location()
997 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in r700_vram_gtt_location()
999 mc->mc_vram_size >> 20, mc->vram_start, in r700_vram_gtt_location()
Drv515.c302 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); in rv515_mc_resume()
303 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); in rv515_mc_resume()
304 WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); in rv515_mc_resume()
305 WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); in rv515_mc_resume()
306 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); in rv515_mc_resume()
327 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | in rv515_mc_program()
330 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); in rv515_mc_program()
Dr520.c148 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | in r520_mc_program()
151 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); in r520_mc_program()
Devergreen.c1249 upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
1251 upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
1253 (u32)rdev->mc.vram_start); in evergreen_mc_resume()
1255 (u32)rdev->mc.vram_start); in evergreen_mc_resume()
1257 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
1258 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); in evergreen_mc_resume()
1348 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in evergreen_mc_program()
1351 rdev->mc.vram_start >> 12); in evergreen_mc_program()
1363 rdev->mc.vram_start >> 12); in evergreen_mc_program()
1374 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; in evergreen_mc_program()
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Dradeon_ttm.c160 man->gpu_offset = rdev->mc.vram_start; in radeon_init_mem_type()
238 old_start += rdev->mc.vram_start; in radeon_move_blit()
249 new_start += rdev->mc.vram_start; in radeon_move_blit()
Drs600.c494 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); in rs600_gart_enable()
832 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | in rs600_mc_program()
835 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); in rs600_mc_program()
Dr600.c1063 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in r600_mc_program()
1066 rdev->mc.vram_start >> 12); in r600_mc_program()
1077 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); in r600_mc_program()
1082 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in r600_mc_program()
1084 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in r600_mc_program()
1145 mc->vram_start = mc->gtt_start - mc->mc_vram_size; in r600_vram_gtt_location()
1152 mc->vram_start = mc->gtt_end + 1; in r600_vram_gtt_location()
1154 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in r600_vram_gtt_location()
1156 mc->mc_vram_size >> 20, mc->vram_start, in r600_vram_gtt_location()
Dsi.c2353 rdev->mc.vram_start >> 12); in si_mc_program()
2359 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in si_mc_program()
2362 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in si_mc_program()
2381 mc->vram_start = base; in si_vram_location()
2387 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in si_vram_location()
2389 mc->mc_vram_size >> 20, mc->vram_start, in si_vram_location()
2398 size_bf = mc->vram_start & ~mc->gtt_base_align; in si_gtt_location()
2404 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; in si_gtt_location()
Dradeon_fb.c252 tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start; in radeonfb_create()
Drs690.c596 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | in rs690_mc_program()
599 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); in rs690_mc_program()
Drs400.c387 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | in rs400_mc_program()
Dr300.c138 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); in rv370_pcie_gart_enable()
1346 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | in r300_mc_program()
Dradeon_object.c241 domain_start = bo->rdev->mc.vram_start; in radeon_bo_pin_restricted()
Dradeon_legacy_crtc.c436 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; in radeon_crtc_do_set_base()
Dr100.c3850 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); in r100_mc_resume()
3852 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); in r100_mc_resume()
3905 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | in r100_mc_program()
Dradeon.h505 u64 vram_start; member
/drivers/video/vermilion/
Dvermilion.c222 vinfo->vram_start = va->phys; in vmlfb_alloc_vram()
240 if (va->phys < vinfo->vram_start) { in vmlfb_alloc_vram()
241 vinfo->vram_start = va->phys; in vmlfb_alloc_vram()
264 (unsigned long)vinfo->vram_start); in vmlfb_alloc_vram()
309 aoffset = offset - (vinfo->vram[i].phys - vinfo->vram_start); in vmlfb_vram_offset()
504 info->fix.smem_start = vinfo->vram_start; in vml_pci_probe()
871 VML_WRITE32(par, VML_DSPCADDR, (u32) vinfo->vram_start + in vmlfb_set_par_locked()
958 VML_WRITE32(par, VML_DSPCADDR, (u32) vinfo->vram_start + in vmlfb_pan_display()
1018 offset += vinfo->vram_start; in vmlfb_mmap()
Dvermilion.h217 u64 vram_start; member
/drivers/gpu/drm/vmwgfx/
Dvmwgfx_buffer.c278 mem->bus.base = dev_priv->vram_start; in vmw_ttm_io_mem_reserve()
Dvmwgfx_drv.c464 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); in vmw_driver_load()
527 dev_priv->vram_start, dev_priv->vram_size / 1024); in vmw_driver_load()
Dvmwgfx_drv.h200 uint32_t vram_start; member
Dvmwgfx_fb.c521 info->apertures->ranges[0].base = vmw_priv->vram_start; in vmw_fb_init()