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Searched refs:BIT (Results 1 – 25 of 38) sorted by relevance

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/include/linux/mfd/abx500/
Dab8500-sysctrl.h83 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
84 #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
85 #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
86 #define AB8500_TURNONSTATUS_RTCALARM BIT(3)
87 #define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
88 #define AB8500_TURNONSTATUS_VBUSDET BIT(5)
89 #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
91 #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
92 #define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2)
97 #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0)
[all …]
/include/linux/usb/
Dlangwell_udc.h54 #define HCC_LEN BIT(17) /* Link power management (LPM) capability */
60 #define HOSTCAP BIT(8) /* host capable */
61 #define DEVCAP BIT(7) /* device capable */
71 #define EXTS_TI1 BIT(4) /* general purpose timer interrupt 1 */
72 #define EXTS_TI1TI0 BIT(3) /* general purpose timer interrupt 0 */
73 #define EXTS_TI1UPI BIT(2) /* USB host periodic interrupt */
74 #define EXTS_TI1UAI BIT(1) /* USB host asynchronous interrupt */
75 #define EXTS_TI1NAKI BIT(0) /* NAK interrupt */
77 #define EXTI_TIE1 BIT(4) /* general purpose timer interrupt enable 1 */
78 #define EXTI_TIE0 BIT(3) /* general purpose timer interrupt enable 0 */
[all …]
/include/linux/mfd/
Dtps65217.h64 #define TPS65217_PPATH_ACSINK_ENABLE BIT(7)
65 #define TPS65217_PPATH_USBSINK_ENABLE BIT(6)
66 #define TPS65217_PPATH_AC_PW_ENABLE BIT(5)
67 #define TPS65217_PPATH_USB_PW_ENABLE BIT(4)
71 #define TPS65217_INT_PBM BIT(6)
72 #define TPS65217_INT_ACM BIT(5)
73 #define TPS65217_INT_USBM BIT(4)
74 #define TPS65217_INT_PBI BIT(2)
75 #define TPS65217_INT_ACI BIT(1)
76 #define TPS65217_INT_USBI BIT(0)
[all …]
Dtps6507x.h23 #define TPS6507X_CHG_USB BIT(7)
24 #define TPS6507X_CHG_AC BIT(6)
25 #define TPS6507X_CHG_USB_PW_ENABLE BIT(5)
26 #define TPS6507X_CHG_AC_PW_ENABLE BIT(4)
27 #define TPS6507X_CHG_AC_CURRENT BIT(2)
28 #define TPS6507X_CHG_USB_CURRENT BIT(0)
31 #define TPS6507X_REG_MASK_AC_USB BIT(7)
32 #define TPS6507X_REG_MASK_TSC BIT(6)
33 #define TPS6507X_REG_MASK_PB_IN BIT(5)
34 #define TPS6507X_REG_TSC_INT BIT(3)
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Ddavinci_voicecodec.h51 #define DAVINCI_VC_CTRL_RSTADC BIT(0)
52 #define DAVINCI_VC_CTRL_RSTDAC BIT(1)
53 #define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4)
54 #define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5)
55 #define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6)
56 #define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7)
57 #define DAVINCI_VC_CTRL_RFIFOEN BIT(8)
58 #define DAVINCI_VC_CTRL_RFIFOCL BIT(9)
59 #define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10)
60 #define DAVINCI_VC_CTRL_WFIFOEN BIT(12)
[all …]
Dwl1273-core.h138 #define WL1273_MODE_RX BIT(0)
139 #define WL1273_MODE_TX BIT(1)
140 #define WL1273_MODE_OFF BIT(2)
141 #define WL1273_MODE_SUSPENDED BIT(3)
143 #define WL1273_RADIO_CHILD BIT(0)
144 #define WL1273_CODEC_CHILD BIT(1)
158 #define WL1273_AUDIO_ENABLE_I2S BIT(0)
159 #define WL1273_AUDIO_ENABLE_ANALOG BIT(1)
223 #define WL1273_FR_EVENT BIT(0)
224 #define WL1273_BL_EVENT BIT(1)
[all …]
Dti_ssp.h61 #define SSP_EARLY_DIN BIT(8)
62 #define SSP_DELAY_DOUT BIT(9)
65 #define SSP_CLK_HIGH BIT(0)
67 #define SSP_DATA_HIGH BIT(1)
69 #define SSP_CS_HIGH BIT(2)
71 #define SSP_OUT_MODE BIT(3)
73 #define SSP_DATA_REG BIT(4)
Ddb8500-prcmu.h20 #define DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0 BIT(0)
21 #define DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD BIT(9)
22 #define DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 BIT(11)
23 #define DB8500_PRCM_GPIOCR_SPI2_SELECT BIT(23)
26 #define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3)
29 #define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
30 #define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
31 #define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
467 #define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
468 #define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
/include/linux/i2c/
Ddm355evm_msp.h30 # define MSP_STATUS_BAD_OFFSET BIT(0)
31 # define MSP_STATUS_BAD_COMMAND BIT(1)
32 # define MSP_STATUS_POWER_ERROR BIT(2)
33 # define MSP_STATUS_RXBUF_OVERRUN BIT(3)
35 # define MSP_RESET_DC5 BIT(0)
36 # define MSP_RESET_TVP5154 BIT(2)
37 # define MSP_RESET_IMAGER BIT(3)
38 # define MSP_RESET_ETHERNET BIT(4)
39 # define MSP_RESET_SYS BIT(5)
40 # define MSP_RESET_AIC33 BIT(7)
[all …]
/include/video/
Dtdfx.h90 #define AUTOINC_DSTX BIT(10)
91 #define AUTOINC_DSTY BIT(11)
97 #define STATUS_RETRACE BIT(6)
98 #define STATUS_BUSY BIT(9)
99 #define MISCINIT1_CLUT_INV BIT(0)
100 #define MISCINIT1_2DBLOCK_DIS BIT(15)
101 #define DRAMINIT0_SGRAM_NUM BIT(26)
102 #define DRAMINIT0_SGRAM_TYPE BIT(27)
103 #define DRAMINIT0_SGRAM_TYPE_MASK (BIT(27) | BIT(28) | BIT(29))
105 #define DRAMINIT1_MEM_SDRAM BIT(30)
[all …]
Dsstfb.h81 # define PCI_EN_INIT_WR BIT(0)
82 # define PCI_EN_FIFO_WR BIT(1)
83 # define PCI_REMAP_DAC BIT(2)
89 # define STATUS_FBI_BUSY BIT(7)
91 # define EN_CLIPPING BIT(0) /* enable clipping */
92 # define EN_RGB_WRITE BIT(9) /* enable writes to rgb area */
93 # define EN_ALPHA_WRITE BIT(10)
94 # define ENGINE_INVERT_Y BIT(17) /* invert Y origin (pipe) */
103 # define EN_PXL_PIPELINE BIT(8) /* pixel pipeline (clip..)*/
104 # define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */
[all …]
/include/linux/
Dedac.h64 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
65 #define DEV_FLAG_X1 BIT(DEV_X1)
66 #define DEV_FLAG_X2 BIT(DEV_X2)
67 #define DEV_FLAG_X4 BIT(DEV_X4)
68 #define DEV_FLAG_X8 BIT(DEV_X8)
69 #define DEV_FLAG_X16 BIT(DEV_X16)
70 #define DEV_FLAG_X32 BIT(DEV_X32)
71 #define DEV_FLAG_X64 BIT(DEV_X64)
133 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
134 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
[all …]
Di2c-omap.h20 #define OMAP_I2C_FLAG_NO_FIFO BIT(0)
21 #define OMAP_I2C_FLAG_SIMPLE_CLOCK BIT(1)
22 #define OMAP_I2C_FLAG_16BIT_DATA_REG BIT(2)
23 #define OMAP_I2C_FLAG_RESET_REGS_POSTIDLE BIT(3)
24 #define OMAP_I2C_FLAG_APPLY_ERRATA_I207 BIT(4)
25 #define OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK BIT(5)
26 #define OMAP_I2C_FLAG_FORCE_19200_INT_CLK BIT(6)
29 #define OMAP_I2C_FLAG_BUS_SHIFT_1 BIT(7)
30 #define OMAP_I2C_FLAG_BUS_SHIFT_2 BIT(8)
Dsmsc911x.h46 #define SMSC911X_USE_16BIT (BIT(0))
47 #define SMSC911X_USE_32BIT (BIT(1))
48 #define SMSC911X_FORCE_INTERNAL_PHY (BIT(2))
49 #define SMSC911X_FORCE_EXTERNAL_PHY (BIT(3))
50 #define SMSC911X_SAVE_MAC_ADDRESS (BIT(4))
60 #define SMSC911X_SWAP_FIFO (BIT(5))
Djz4740-adc.h18 #define JZ_ADC_CONFIG_SPZZ BIT(31)
19 #define JZ_ADC_CONFIG_EX_IN BIT(30)
21 #define JZ_ADC_CONFIG_DMA_ENABLE BIT(15)
25 #define JZ_ADC_CONFIG_BAT_MB BIT(4)
Dclk-provider.h36 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
37 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
38 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
39 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
40 #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
181 #define CLK_GATE_SET_TO_DISABLE BIT(0)
218 #define CLK_DIVIDER_ONE_BASED BIT(0)
219 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
252 #define CLK_MUX_INDEX_ONE BIT(0)
253 #define CLK_MUX_INDEX_BIT BIT(1)
Dclk.h42 #define PRE_RATE_CHANGE BIT(0)
43 #define POST_RATE_CHANGE BIT(1)
44 #define ABORT_RATE_CHANGE BIT(2)
/include/media/
Domap1_camera.h31 #define OMAP1_CAMERA_LCLK_RISING BIT(0)
32 #define OMAP1_CAMERA_RST_LOW BIT(1)
33 #define OMAP1_CAMERA_RST_HIGH BIT(2)
/include/media/davinci/
Dvpbe_venc.h26 #define VENC_END_OF_FRAME BIT(0)
27 #define VENC_FIRST_FIELD BIT(1)
28 #define VENC_SECOND_FIELD BIT(2)
/include/net/
Dmac80211.h389 IEEE80211_TX_CTL_REQ_TX_STATUS = BIT(0),
390 IEEE80211_TX_CTL_ASSIGN_SEQ = BIT(1),
391 IEEE80211_TX_CTL_NO_ACK = BIT(2),
392 IEEE80211_TX_CTL_CLEAR_PS_FILT = BIT(3),
393 IEEE80211_TX_CTL_FIRST_FRAGMENT = BIT(4),
394 IEEE80211_TX_CTL_SEND_AFTER_DTIM = BIT(5),
395 IEEE80211_TX_CTL_AMPDU = BIT(6),
396 IEEE80211_TX_CTL_INJECTED = BIT(7),
397 IEEE80211_TX_STAT_TX_FILTERED = BIT(8),
398 IEEE80211_TX_STAT_ACK = BIT(9),
[all …]
Dcfg80211.h453 STATION_PARAM_APPLY_UAPSD = BIT(0),
716 MPATH_INFO_FRAME_QLEN = BIT(0),
717 MPATH_INFO_SN = BIT(1),
718 MPATH_INFO_METRIC = BIT(2),
719 MPATH_INFO_EXPTIME = BIT(3),
720 MPATH_INFO_DISCOVERY_TIMEOUT = BIT(4),
721 MPATH_INFO_DISCOVERY_RETRIES = BIT(5),
722 MPATH_INFO_FLAGS = BIT(6),
1074 ASSOC_REQ_DISABLE_HT = BIT(0),
1772 WIPHY_FLAG_CUSTOM_REGULATORY = BIT(0),
[all …]
/include/scsi/
Dosd_sense.h209 OSD_CFB_COMMAND = BIT(4),
210 OSD_CFB_CMD_CAP_VERIFIED = BIT(5),
211 OSD_CFB_VALIDATION = BIT(7),
212 OSD_CFB_IMP_ST_ATT = BIT(12),
213 OSD_CFB_SET_ATT = BIT(20),
214 OSD_CFB_SA_CAP_VERIFIED = BIT(21),
215 OSD_CFB_GET_ATT = BIT(28),
216 OSD_CFB_GA_CAP_VERIFIED = BIT(29),
Dosd_protocol.h525 OSD_SEC_CAP_APPEND = BIT(0),
526 OSD_SEC_CAP_OBJ_MGMT = BIT(1),
527 OSD_SEC_CAP_REMOVE = BIT(2),
528 OSD_SEC_CAP_CREATE = BIT(3),
529 OSD_SEC_CAP_SET_ATTR = BIT(4),
530 OSD_SEC_CAP_GET_ATTR = BIT(5),
531 OSD_SEC_CAP_WRITE = BIT(6),
532 OSD_SEC_CAP_READ = BIT(7),
534 OSD_SEC_CAP_NONE1 = BIT(8),
535 OSD_SEC_CAP_NONE2 = BIT(9),
[all …]
/include/linux/bcma/
Dbcma_driver_chipcommon.h312 #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
313 #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
314 #define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */
315 #define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */
316 #define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */
317 #define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */
318 #define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */
319 #define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout …
320 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */
321 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
[all …]
/include/linux/mmc/
Ddw_mmc.h196 #define DW_MCI_QUIRK_IDMAC_DTO BIT(0)
198 #define DW_MCI_QUIRK_RETRY_DELAY BIT(1)
200 #define DW_MCI_QUIRK_HIGHSPEED BIT(2)
202 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)

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