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Searched refs:CM_CLKEN (Results 1 – 8 of 8) sorted by relevance

/arch/arm/mach-omap2/
Dclkt2xxx_apll.c52 cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); in omap2_clk_apll_enable()
59 omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); in omap2_clk_apll_enable()
106 cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); in omap2_clk_apll_disable()
108 omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); in omap2_clk_apll_disable()
Dcm2xxx_3xxx.h52 #define CM_CLKEN CM_FCLKEN macro
Dclock3xxx_data.c415 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
545 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
572 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
593 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
658 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
761 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
848 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
875 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
900 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
Dcontrol.c315 omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); in omap3_save_scratchpad_contents()
Dclock2420_data.c114 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
142 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
153 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
Dsram242x.S321 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
Dsram243x.S321 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
Dclock2430_data.c113 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
141 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
152 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),