1 /* arch/arm/mach-s3c2410/include/mach/dma.h
2 *
3 * Copyright (C) 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #ifndef __ASM_ARCH_DMA_H
14 #define __ASM_ARCH_DMA_H __FILE__
15
16 #include <linux/device.h>
17
18 #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
19
20 /* We use `virtual` dma channels to hide the fact we have only a limited
21 * number of DMA channels, and not of all of them (dependent on the device)
22 * can be attached to any DMA source. We therefore let the DMA core handle
23 * the allocation of hardware channels to clients.
24 */
25
26 enum dma_ch {
27 DMACH_DT_PROP = -1, /* not yet supported, do not use */
28 DMACH_XD0 = 0,
29 DMACH_XD1,
30 DMACH_SDI,
31 DMACH_SPI0,
32 DMACH_SPI1,
33 DMACH_UART0,
34 DMACH_UART1,
35 DMACH_UART2,
36 DMACH_TIMER,
37 DMACH_I2S_IN,
38 DMACH_I2S_OUT,
39 DMACH_PCM_IN,
40 DMACH_PCM_OUT,
41 DMACH_MIC_IN,
42 DMACH_USB_EP1,
43 DMACH_USB_EP2,
44 DMACH_USB_EP3,
45 DMACH_USB_EP4,
46 DMACH_UART0_SRC2, /* s3c2412 second uart sources */
47 DMACH_UART1_SRC2,
48 DMACH_UART2_SRC2,
49 DMACH_UART3, /* s3c2443 has extra uart */
50 DMACH_UART3_SRC2,
51 DMACH_MAX, /* the end entry */
52 };
53
samsung_dma_has_circular(void)54 static inline bool samsung_dma_has_circular(void)
55 {
56 return false;
57 }
58
samsung_dma_is_dmadev(void)59 static inline bool samsung_dma_is_dmadev(void)
60 {
61 return false;
62 }
63
64 #include <plat/dma.h>
65
66 #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
67
68 /* we have 4 dma channels */
69 #if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
70 #define S3C_DMA_CHANNELS (4)
71 #else
72 #define S3C_DMA_CHANNELS (6)
73 #endif
74
75 /* types */
76
77 enum s3c2410_dma_state {
78 S3C2410_DMA_IDLE,
79 S3C2410_DMA_RUNNING,
80 S3C2410_DMA_PAUSED
81 };
82
83 /* enum s3c2410_dma_loadst
84 *
85 * This represents the state of the DMA engine, wrt to the loaded / running
86 * transfers. Since we don't have any way of knowing exactly the state of
87 * the DMA transfers, we need to know the state to make decisions on wether
88 * we can
89 *
90 * S3C2410_DMA_NONE
91 *
92 * There are no buffers loaded (the channel should be inactive)
93 *
94 * S3C2410_DMA_1LOADED
95 *
96 * There is one buffer loaded, however it has not been confirmed to be
97 * loaded by the DMA engine. This may be because the channel is not
98 * yet running, or the DMA driver decided that it was too costly to
99 * sit and wait for it to happen.
100 *
101 * S3C2410_DMA_1RUNNING
102 *
103 * The buffer has been confirmed running, and not finisged
104 *
105 * S3C2410_DMA_1LOADED_1RUNNING
106 *
107 * There is a buffer waiting to be loaded by the DMA engine, and one
108 * currently running.
109 */
110
111 enum s3c2410_dma_loadst {
112 S3C2410_DMALOAD_NONE,
113 S3C2410_DMALOAD_1LOADED,
114 S3C2410_DMALOAD_1RUNNING,
115 S3C2410_DMALOAD_1LOADED_1RUNNING,
116 };
117
118
119 /* flags */
120
121 #define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
122 * waiting for reloads */
123 #define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
124
125 #define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */
126
127 /* dma buffer */
128
129 struct s3c2410_dma_buf;
130
131 /* s3c2410_dma_buf
132 *
133 * internally used buffer structure to describe a queued or running
134 * buffer.
135 */
136
137 struct s3c2410_dma_buf {
138 struct s3c2410_dma_buf *next;
139 int magic; /* magic */
140 int size; /* buffer size in bytes */
141 dma_addr_t data; /* start of DMA data */
142 dma_addr_t ptr; /* where the DMA got to [1] */
143 void *id; /* client's id */
144 };
145
146 /* [1] is this updated for both recv/send modes? */
147
148 struct s3c2410_dma_stats {
149 unsigned long loads;
150 unsigned long timeout_longest;
151 unsigned long timeout_shortest;
152 unsigned long timeout_avg;
153 unsigned long timeout_failed;
154 };
155
156 struct s3c2410_dma_map;
157
158 /* struct s3c2410_dma_chan
159 *
160 * full state information for each DMA channel
161 */
162
163 struct s3c2410_dma_chan {
164 /* channel state flags and information */
165 unsigned char number; /* number of this dma channel */
166 unsigned char in_use; /* channel allocated */
167 unsigned char irq_claimed; /* irq claimed for channel */
168 unsigned char irq_enabled; /* irq enabled for channel */
169 unsigned char xfer_unit; /* size of an transfer */
170
171 /* channel state */
172
173 enum s3c2410_dma_state state;
174 enum s3c2410_dma_loadst load_state;
175 struct s3c2410_dma_client *client;
176
177 /* channel configuration */
178 enum dma_data_direction source;
179 enum dma_ch req_ch;
180 unsigned long dev_addr;
181 unsigned long load_timeout;
182 unsigned int flags; /* channel flags */
183
184 struct s3c24xx_dma_map *map; /* channel hw maps */
185
186 /* channel's hardware position and configuration */
187 void __iomem *regs; /* channels registers */
188 void __iomem *addr_reg; /* data address register */
189 unsigned int irq; /* channel irq */
190 unsigned long dcon; /* default value of DCON */
191
192 /* driver handles */
193 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
194 s3c2410_dma_opfn_t op_fn; /* channel op callback */
195
196 /* stats gathering */
197 struct s3c2410_dma_stats *stats;
198 struct s3c2410_dma_stats stats_store;
199
200 /* buffer list and information */
201 struct s3c2410_dma_buf *curr; /* current dma buffer */
202 struct s3c2410_dma_buf *next; /* next buffer to load */
203 struct s3c2410_dma_buf *end; /* end of queue */
204
205 /* system device */
206 struct device dev;
207 };
208
209 typedef unsigned long dma_device_t;
210
211 #endif /* __ASM_ARCH_DMA_H */
212