1 /*
2 * File: arch/blackfin/mach-bf561/acvilon.c
3 * Based on: arch/blackfin/mach-bf561/ezkit.c
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 * Copyright 2009 CJSC "NII STT"
12 *
13 * Bugs:
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 *
30 *
31 * For more information about Acvilon BF561 SoM please
32 * go to http://www.niistt.ru/
33 *
34 */
35
36 #include <linux/device.h>
37 #include <linux/platform_device.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/partitions.h>
40 #include <linux/mtd/physmap.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/plat-ram.h>
43 #include <linux/spi/spi.h>
44 #include <linux/spi/flash.h>
45 #include <linux/irq.h>
46 #include <linux/interrupt.h>
47 #include <linux/jiffies.h>
48 #include <linux/i2c-pca-platform.h>
49 #include <linux/delay.h>
50 #include <linux/io.h>
51 #include <asm/dma.h>
52 #include <asm/bfin5xx_spi.h>
53 #include <asm/portmux.h>
54 #include <asm/dpmc.h>
55 #include <asm/cacheflush.h>
56 #include <linux/i2c.h>
57
58 /*
59 * Name the Board for the /proc/cpuinfo
60 */
61 const char bfin_board_name[] = "Acvilon board";
62
63 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
64 #include <linux/usb/isp1760.h>
65 static struct resource bfin_isp1760_resources[] = {
66 [0] = {
67 .start = 0x20000000,
68 .end = 0x20000000 + 0x000fffff,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = IRQ_PF15,
73 .end = IRQ_PF15,
74 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
75 },
76 };
77
78 static struct isp1760_platform_data isp1760_priv = {
79 .is_isp1761 = 0,
80 .port1_disable = 0,
81 .bus_width_16 = 1,
82 .port1_otg = 0,
83 .analog_oc = 0,
84 .dack_polarity_high = 0,
85 .dreq_polarity_high = 0,
86 };
87
88 static struct platform_device bfin_isp1760_device = {
89 .name = "isp1760-hcd",
90 .id = 0,
91 .dev = {
92 .platform_data = &isp1760_priv,
93 },
94 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
95 .resource = bfin_isp1760_resources,
96 };
97 #endif
98
99 static struct resource bfin_i2c_pca_resources[] = {
100 {
101 .name = "pca9564-regs",
102 .start = 0x2C000000,
103 .end = 0x2C000000 + 16,
104 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
105 }, {
106
107 .start = IRQ_PF8,
108 .end = IRQ_PF8,
109 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
110 },
111 };
112
113 struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
114 .gpio = -1,
115 .i2c_clock_speed = 330000,
116 .timeout = HZ,
117 };
118
119 /* PCA9564 I2C Bus driver */
120 static struct platform_device bfin_i2c_pca_device = {
121 .name = "i2c-pca-platform",
122 .id = 0,
123 .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources),
124 .resource = bfin_i2c_pca_resources,
125 .dev = {
126 .platform_data = &pca9564_platform_data,
127 }
128 };
129
130 /* I2C devices fitted. */
131 static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
132 {
133 I2C_BOARD_INFO("ds1339", 0x68),
134 },
135 {
136 I2C_BOARD_INFO("tcn75", 0x49),
137 },
138 };
139
140 #if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
141 static struct platdata_mtd_ram mtd_ram_data = {
142 .mapname = "rootfs(RAM)",
143 .bankwidth = 4,
144 };
145
146 static struct resource mtd_ram_resource = {
147 .start = 0x4000000,
148 .end = 0x5ffffff,
149 .flags = IORESOURCE_MEM,
150 };
151
152 static struct platform_device mtd_ram_device = {
153 .name = "mtd-ram",
154 .id = 0,
155 .dev = {
156 .platform_data = &mtd_ram_data,
157 },
158 .num_resources = 1,
159 .resource = &mtd_ram_resource,
160 };
161 #endif
162
163 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
164 #include <linux/smsc911x.h>
165 static struct resource smsc911x_resources[] = {
166 {
167 .name = "smsc911x-memory",
168 .start = 0x28000000,
169 .end = 0x28000000 + 0xFF,
170 .flags = IORESOURCE_MEM,
171 },
172 {
173 .start = IRQ_PF7,
174 .end = IRQ_PF7,
175 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
176 },
177 };
178
179 static struct smsc911x_platform_config smsc911x_config = {
180 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
181 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
182 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
183 .phy_interface = PHY_INTERFACE_MODE_MII,
184 };
185
186 static struct platform_device smsc911x_device = {
187 .name = "smsc911x",
188 .id = 0,
189 .num_resources = ARRAY_SIZE(smsc911x_resources),
190 .resource = smsc911x_resources,
191 .dev = {
192 .platform_data = &smsc911x_config,
193 },
194 };
195 #endif
196
197 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
198 #ifdef CONFIG_SERIAL_BFIN_UART0
199 static struct resource bfin_uart0_resources[] = {
200 {
201 .start = BFIN_UART_THR,
202 .end = BFIN_UART_GCTL + 2,
203 .flags = IORESOURCE_MEM,
204 },
205 {
206 .start = IRQ_UART_TX,
207 .end = IRQ_UART_TX,
208 .flags = IORESOURCE_IRQ,
209 },
210 {
211 .start = IRQ_UART_RX,
212 .end = IRQ_UART_RX,
213 .flags = IORESOURCE_IRQ,
214 },
215 {
216 .start = IRQ_UART_ERROR,
217 .end = IRQ_UART_ERROR,
218 .flags = IORESOURCE_IRQ,
219 },
220 {
221 .start = CH_UART_TX,
222 .end = CH_UART_TX,
223 .flags = IORESOURCE_DMA,
224 },
225 {
226 .start = CH_UART_RX,
227 .end = CH_UART_RX,
228 .flags = IORESOURCE_DMA,
229 },
230 };
231
232 static unsigned short bfin_uart0_peripherals[] = {
233 P_UART0_TX, P_UART0_RX, 0
234 };
235
236 static struct platform_device bfin_uart0_device = {
237 .name = "bfin-uart",
238 .id = 0,
239 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
240 .resource = bfin_uart0_resources,
241 .dev = {
242 /* Passed to driver */
243 .platform_data = &bfin_uart0_peripherals,
244 },
245 };
246 #endif
247 #endif
248
249 #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
250
251 const char *part_probes[] = { "cmdlinepart", NULL };
252
253 static struct mtd_partition bfin_plat_nand_partitions[] = {
254 {
255 .name = "params(nand)",
256 .size = 32 * 1024 * 1024,
257 .offset = 0,
258 }, {
259 .name = "userfs(nand)",
260 .size = MTDPART_SIZ_FULL,
261 .offset = MTDPART_OFS_APPEND,
262 },
263 };
264
265 #define BFIN_NAND_PLAT_CLE 2
266 #define BFIN_NAND_PLAT_ALE 3
267
bfin_plat_nand_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)268 static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
269 unsigned int ctrl)
270 {
271 struct nand_chip *this = mtd->priv;
272
273 if (cmd == NAND_CMD_NONE)
274 return;
275
276 if (ctrl & NAND_CLE)
277 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
278 else
279 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
280 }
281
282 #define BFIN_NAND_PLAT_READY GPIO_PF10
bfin_plat_nand_dev_ready(struct mtd_info * mtd)283 static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
284 {
285 return gpio_get_value(BFIN_NAND_PLAT_READY);
286 }
287
288 static struct platform_nand_data bfin_plat_nand_data = {
289 .chip = {
290 .nr_chips = 1,
291 .chip_delay = 30,
292 .part_probe_types = part_probes,
293 .partitions = bfin_plat_nand_partitions,
294 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
295 },
296 .ctrl = {
297 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
298 .dev_ready = bfin_plat_nand_dev_ready,
299 },
300 };
301
302 #define MAX(x, y) (x > y ? x : y)
303 static struct resource bfin_plat_nand_resources = {
304 .start = 0x24000000,
305 .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
306 .flags = IORESOURCE_MEM,
307 };
308
309 static struct platform_device bfin_async_nand_device = {
310 .name = "gen_nand",
311 .id = -1,
312 .num_resources = 1,
313 .resource = &bfin_plat_nand_resources,
314 .dev = {
315 .platform_data = &bfin_plat_nand_data,
316 },
317 };
318
bfin_plat_nand_init(void)319 static void bfin_plat_nand_init(void)
320 {
321 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
322 }
323 #else
bfin_plat_nand_init(void)324 static void bfin_plat_nand_init(void)
325 {
326 }
327 #endif
328
329 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
330 static struct mtd_partition bfin_spi_dataflash_partitions[] = {
331 {
332 .name = "bootloader",
333 .size = 0x4200,
334 .offset = 0,
335 .mask_flags = MTD_CAP_ROM},
336 {
337 .name = "u-boot",
338 .size = 0x42000,
339 .offset = MTDPART_OFS_APPEND,
340 },
341 {
342 .name = "u-boot(params)",
343 .size = 0x4200,
344 .offset = MTDPART_OFS_APPEND,
345 },
346 {
347 .name = "kernel",
348 .size = 0x294000,
349 .offset = MTDPART_OFS_APPEND,
350 },
351 {
352 .name = "params",
353 .size = 0x42000,
354 .offset = MTDPART_OFS_APPEND,
355 },
356 {
357 .name = "rootfs",
358 .size = MTDPART_SIZ_FULL,
359 .offset = MTDPART_OFS_APPEND,
360 }
361 };
362
363 static struct flash_platform_data bfin_spi_dataflash_data = {
364 .name = "SPI Dataflash",
365 .parts = bfin_spi_dataflash_partitions,
366 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
367 };
368
369 /* DataFlash chip */
370 static struct bfin5xx_spi_chip data_flash_chip_info = {
371 .enable_dma = 0, /* use dma transfer with this chip */
372 };
373 #endif
374
375 #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
376 /* SPI (0) */
377 static struct resource bfin_spi0_resource[] = {
378 [0] = {
379 .start = SPI0_REGBASE,
380 .end = SPI0_REGBASE + 0xFF,
381 .flags = IORESOURCE_MEM,
382 },
383 [1] = {
384 .start = CH_SPI,
385 .end = CH_SPI,
386 .flags = IORESOURCE_DMA,
387 },
388 [2] = {
389 .start = IRQ_SPI,
390 .end = IRQ_SPI,
391 .flags = IORESOURCE_IRQ,
392 },
393 };
394
395 /* SPI controller data */
396 static struct bfin5xx_spi_master bfin_spi0_info = {
397 .num_chipselect = 8,
398 .enable_dma = 1, /* master has the ability to do dma transfer */
399 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
400 };
401
402 static struct platform_device bfin_spi0_device = {
403 .name = "bfin-spi",
404 .id = 0, /* Bus number */
405 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
406 .resource = bfin_spi0_resource,
407 .dev = {
408 .platform_data = &bfin_spi0_info, /* Passed to driver */
409 },
410 };
411 #endif
412
413 static struct spi_board_info bfin_spi_board_info[] __initdata = {
414 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
415 {
416 .modalias = "spidev",
417 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
418 .bus_num = 0,
419 .chip_select = 3,
420 },
421 #endif
422 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
423 { /* DataFlash chip */
424 .modalias = "mtd_dataflash",
425 .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
426 .bus_num = 0, /* Framework bus number */
427 .chip_select = 2, /* Framework chip select */
428 .platform_data = &bfin_spi_dataflash_data,
429 .controller_data = &data_flash_chip_info,
430 .mode = SPI_MODE_3,
431 },
432 #endif
433 };
434
435 static struct resource bfin_gpios_resources = {
436 .start = 31,
437 /* .end = MAX_BLACKFIN_GPIOS - 1, */
438 .end = 32,
439 .flags = IORESOURCE_IRQ,
440 };
441
442 static struct platform_device bfin_gpios_device = {
443 .name = "simple-gpio",
444 .id = -1,
445 .num_resources = 1,
446 .resource = &bfin_gpios_resources,
447 };
448
449 static const unsigned int cclk_vlev_datasheet[] = {
450 VRPAIR(VLEV_085, 250000000),
451 VRPAIR(VLEV_090, 300000000),
452 VRPAIR(VLEV_095, 313000000),
453 VRPAIR(VLEV_100, 350000000),
454 VRPAIR(VLEV_105, 400000000),
455 VRPAIR(VLEV_110, 444000000),
456 VRPAIR(VLEV_115, 450000000),
457 VRPAIR(VLEV_120, 475000000),
458 VRPAIR(VLEV_125, 500000000),
459 VRPAIR(VLEV_130, 600000000),
460 };
461
462 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
463 .tuple_tab = cclk_vlev_datasheet,
464 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
465 .vr_settling_time = 25 /* us */ ,
466 };
467
468 static struct platform_device bfin_dpmc = {
469 .name = "bfin dpmc",
470 .dev = {
471 .platform_data = &bfin_dmpc_vreg_data,
472 },
473 };
474
475 static struct platform_device *acvilon_devices[] __initdata = {
476 &bfin_dpmc,
477
478 #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
479 &bfin_spi0_device,
480 #endif
481
482 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
483 #ifdef CONFIG_SERIAL_BFIN_UART0
484 &bfin_uart0_device,
485 #endif
486 #endif
487
488 &bfin_gpios_device,
489
490 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
491 &smsc911x_device,
492 #endif
493
494 &bfin_i2c_pca_device,
495
496 #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
497 &bfin_async_nand_device,
498 #endif
499
500 #if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
501 &mtd_ram_device,
502 #endif
503
504 };
505
acvilon_init(void)506 static int __init acvilon_init(void)
507 {
508 int ret;
509
510 printk(KERN_INFO "%s(): registering device resources\n", __func__);
511
512 bfin_plat_nand_init();
513 ret =
514 platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices));
515 if (ret < 0)
516 return ret;
517
518 i2c_register_board_info(0, acvilon_i2c_devs,
519 ARRAY_SIZE(acvilon_i2c_devs));
520
521 bfin_write_FIO0_FLAG_C(1 << 14);
522 msleep(5);
523 bfin_write_FIO0_FLAG_S(1 << 14);
524
525 spi_register_board_info(bfin_spi_board_info,
526 ARRAY_SIZE(bfin_spi_board_info));
527 return 0;
528 }
529
530 arch_initcall(acvilon_init);
531
532 static struct platform_device *acvilon_early_devices[] __initdata = {
533 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
534 #ifdef CONFIG_SERIAL_BFIN_UART0
535 &bfin_uart0_device,
536 #endif
537 #endif
538 };
539
native_machine_early_platform_add_devices(void)540 void __init native_machine_early_platform_add_devices(void)
541 {
542 printk(KERN_INFO "register early platform devices\n");
543 early_platform_add_devices(acvilon_early_devices,
544 ARRAY_SIZE(acvilon_early_devices));
545 }
546