1 #ifndef _PARISC_PGTABLE_H
2 #define _PARISC_PGTABLE_H
3
4 #include <asm-generic/4level-fixup.h>
5
6 #include <asm/fixmap.h>
7
8 #ifndef __ASSEMBLY__
9 /*
10 * we simulate an x86-style page table for the linux mm code
11 */
12
13 #include <linux/bitops.h>
14 #include <linux/spinlock.h>
15 #include <linux/mm_types.h>
16 #include <asm/processor.h>
17 #include <asm/cache.h>
18
19 /*
20 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
21 * memory. For the return value to be meaningful, ADDR must be >=
22 * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
23 * require a hash-, or multi-level tree-lookup or something of that
24 * sort) but it guarantees to return TRUE only if accessing the page
25 * at that address does not cause an error. Note that there may be
26 * addresses for which kern_addr_valid() returns FALSE even though an
27 * access would not cause an error (e.g., this is typically true for
28 * memory mapped I/O regions.
29 *
30 * XXX Need to implement this for parisc.
31 */
32 #define kern_addr_valid(addr) (1)
33
34 /* Certain architectures need to do special things when PTEs
35 * within a page table are directly modified. Thus, the following
36 * hook is made available.
37 */
38 #define set_pte(pteptr, pteval) \
39 do{ \
40 *(pteptr) = (pteval); \
41 } while(0)
42
43 extern void purge_tlb_entries(struct mm_struct *, unsigned long);
44
45 #define set_pte_at(mm, addr, ptep, pteval) \
46 do { \
47 set_pte(ptep, pteval); \
48 purge_tlb_entries(mm, addr); \
49 } while (0)
50
51 #endif /* !__ASSEMBLY__ */
52
53 #include <asm/page.h>
54
55 #define pte_ERROR(e) \
56 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
57 #define pmd_ERROR(e) \
58 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e))
59 #define pgd_ERROR(e) \
60 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e))
61
62 /* This is the size of the initially mapped kernel memory */
63 #define KERNEL_INITIAL_ORDER 24 /* 0 to 1<<24 = 16MB */
64 #define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER)
65
66 #if defined(CONFIG_64BIT) && defined(CONFIG_PARISC_PAGE_SIZE_4KB)
67 #define PT_NLEVELS 3
68 #define PGD_ORDER 1 /* Number of pages per pgd */
69 #define PMD_ORDER 1 /* Number of pages per pmd */
70 #define PGD_ALLOC_ORDER 2 /* first pgd contains pmd */
71 #else
72 #define PT_NLEVELS 2
73 #define PGD_ORDER 1 /* Number of pages per pgd */
74 #define PGD_ALLOC_ORDER PGD_ORDER
75 #endif
76
77 /* Definitions for 3rd level (we use PLD here for Page Lower directory
78 * because PTE_SHIFT is used lower down to mean shift that has to be
79 * done to get usable bits out of the PTE) */
80 #define PLD_SHIFT PAGE_SHIFT
81 #define PLD_SIZE PAGE_SIZE
82 #define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY)
83 #define PTRS_PER_PTE (1UL << BITS_PER_PTE)
84
85 /* Definitions for 2nd level */
86 #define pgtable_cache_init() do { } while (0)
87
88 #define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE)
89 #define PMD_SIZE (1UL << PMD_SHIFT)
90 #define PMD_MASK (~(PMD_SIZE-1))
91 #if PT_NLEVELS == 3
92 #define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
93 #else
94 #define BITS_PER_PMD 0
95 #endif
96 #define PTRS_PER_PMD (1UL << BITS_PER_PMD)
97
98 /* Definitions for 1st level */
99 #define PGDIR_SHIFT (PMD_SHIFT + BITS_PER_PMD)
100 #if (PGDIR_SHIFT + PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG
101 #define BITS_PER_PGD (BITS_PER_LONG - PGDIR_SHIFT)
102 #else
103 #define BITS_PER_PGD (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY)
104 #endif
105 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
106 #define PGDIR_MASK (~(PGDIR_SIZE-1))
107 #define PTRS_PER_PGD (1UL << BITS_PER_PGD)
108 #define USER_PTRS_PER_PGD PTRS_PER_PGD
109
110 #ifdef CONFIG_64BIT
111 #define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD)
112 #define MAX_ADDRESS (1UL << MAX_ADDRBITS)
113 #define SPACEID_SHIFT (MAX_ADDRBITS - 32)
114 #else
115 #define MAX_ADDRBITS (BITS_PER_LONG)
116 #define MAX_ADDRESS (1UL << MAX_ADDRBITS)
117 #define SPACEID_SHIFT 0
118 #endif
119
120 /* This calculates the number of initial pages we need for the initial
121 * page tables */
122 #if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT)
123 # define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
124 #else
125 # define PT_INITIAL (1) /* all initial PTEs fit into one page */
126 #endif
127
128 /*
129 * pgd entries used up by user/kernel:
130 */
131
132 #define FIRST_USER_ADDRESS 0
133
134 /* NB: The tlb miss handlers make certain assumptions about the order */
135 /* of the following bits, so be careful (One example, bits 25-31 */
136 /* are moved together in one instruction). */
137
138 #define _PAGE_READ_BIT 31 /* (0x001) read access allowed */
139 #define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */
140 #define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */
141 #define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */
142 #define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */
143 #define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */
144 #define _PAGE_FILE_BIT _PAGE_DIRTY_BIT /* overload this bit */
145 #define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */
146 #define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */
147 #define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */
148 #define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */
149 /* bit 21 was formerly the FLUSH bit but is now unused */
150 #define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */
151
152 /* N.B. The bits are defined in terms of a 32 bit word above, so the */
153 /* following macro is ok for both 32 and 64 bit. */
154
155 #define xlate_pabit(x) (31 - x)
156
157 /* this defines the shift to the usable bits in the PTE it is set so
158 * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set
159 * to zero */
160 #define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT)
161
162 /* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
163 #define PFN_PTE_SHIFT 12
164
165
166 /* this is how many bits may be used by the file functions */
167 #define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_SHIFT)
168
169 #define pte_to_pgoff(pte) (pte_val(pte) >> PTE_SHIFT)
170 #define pgoff_to_pte(off) ((pte_t) { ((off) << PTE_SHIFT) | _PAGE_FILE })
171
172 #define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT))
173 #define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT))
174 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
175 #define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT))
176 #define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT))
177 #define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT))
178 #define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT))
179 #define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT))
180 #define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT))
181 #define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT))
182 #define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT))
183 #define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT))
184 #define _PAGE_FILE (1 << xlate_pabit(_PAGE_FILE_BIT))
185
186 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)
187 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
188 #define _PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED)
189 #define _PAGE_KERNEL_EXEC (_PAGE_KERNEL_RO | _PAGE_EXEC)
190 #define _PAGE_KERNEL_RWX (_PAGE_KERNEL_EXEC | _PAGE_WRITE)
191 #define _PAGE_KERNEL (_PAGE_KERNEL_RO | _PAGE_WRITE)
192
193 /* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
194 * are page-aligned, we don't care about the PAGE_OFFSET bits, except
195 * for a few meta-information bits, so we shift the address to be
196 * able to effectively address 40/42/44-bits of physical address space
197 * depending on 4k/16k/64k PAGE_SIZE */
198 #define _PxD_PRESENT_BIT 31
199 #define _PxD_ATTACHED_BIT 30
200 #define _PxD_VALID_BIT 29
201
202 #define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT))
203 #define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT))
204 #define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT))
205 #define PxD_FLAG_MASK (0xf)
206 #define PxD_FLAG_SHIFT (4)
207 #define PxD_VALUE_SHIFT (8) /* (PAGE_SHIFT-PxD_FLAG_SHIFT) */
208
209 #ifndef __ASSEMBLY__
210
211 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
212 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_ACCESSED)
213 /* Others seem to make this executable, I don't know if that's correct
214 or not. The stack is mapped this way though so this is necessary
215 in the short term - dhd@linuxcare.com, 2000-08-08 */
216 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_ACCESSED)
217 #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE | _PAGE_ACCESSED)
218 #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC |_PAGE_ACCESSED)
219 #define PAGE_COPY PAGE_EXECREAD
220 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC |_PAGE_ACCESSED)
221 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
222 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC)
223 #define PAGE_KERNEL_RWX __pgprot(_PAGE_KERNEL_RWX)
224 #define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO)
225 #define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
226 #define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_GATEWAY| _PAGE_READ)
227
228
229 /*
230 * We could have an execute only page using "gateway - promote to priv
231 * level 3", but that is kind of silly. So, the way things are defined
232 * now, we must always have read permission for pages with execute
233 * permission. For the fun of it we'll go ahead and support write only
234 * pages.
235 */
236
237 /*xwr*/
238 #define __P000 PAGE_NONE
239 #define __P001 PAGE_READONLY
240 #define __P010 __P000 /* copy on write */
241 #define __P011 __P001 /* copy on write */
242 #define __P100 PAGE_EXECREAD
243 #define __P101 PAGE_EXECREAD
244 #define __P110 __P100 /* copy on write */
245 #define __P111 __P101 /* copy on write */
246
247 #define __S000 PAGE_NONE
248 #define __S001 PAGE_READONLY
249 #define __S010 PAGE_WRITEONLY
250 #define __S011 PAGE_SHARED
251 #define __S100 PAGE_EXECREAD
252 #define __S101 PAGE_EXECREAD
253 #define __S110 PAGE_RWX
254 #define __S111 PAGE_RWX
255
256
257 extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
258
259 /* initial page tables for 0-8MB for kernel */
260
261 extern pte_t pg0[];
262
263 /* zero page used for uninitialized stuff */
264
265 extern unsigned long *empty_zero_page;
266
267 /*
268 * ZERO_PAGE is a global shared page that is always zero: used
269 * for zero-mapped memory areas etc..
270 */
271
272 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
273
274 #define pte_none(x) (pte_val(x) == 0)
275 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
276 #define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0)
277
278 #define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK)
279 #define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
280 #define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK)
281 #define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
282
283 #if PT_NLEVELS == 3
284 /* The first entry of the permanent pmd is not there if it contains
285 * the gateway marker */
286 #define pmd_none(x) (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED)
287 #else
288 #define pmd_none(x) (!pmd_val(x))
289 #endif
290 #define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID))
291 #define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT)
pmd_clear(pmd_t * pmd)292 static inline void pmd_clear(pmd_t *pmd) {
293 #if PT_NLEVELS == 3
294 if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
295 /* This is the entry pointing to the permanent pmd
296 * attached to the pgd; cannot clear it */
297 __pmd_val_set(*pmd, PxD_FLAG_ATTACHED);
298 else
299 #endif
300 __pmd_val_set(*pmd, 0);
301 }
302
303
304
305 #if PT_NLEVELS == 3
306 #define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_address(pgd)))
307 #define pgd_page(pgd) virt_to_page((void *)pgd_page_vaddr(pgd))
308
309 /* For 64 bit we have three level tables */
310
311 #define pgd_none(x) (!pgd_val(x))
312 #define pgd_bad(x) (!(pgd_flag(x) & PxD_FLAG_VALID))
313 #define pgd_present(x) (pgd_flag(x) & PxD_FLAG_PRESENT)
pgd_clear(pgd_t * pgd)314 static inline void pgd_clear(pgd_t *pgd) {
315 #if PT_NLEVELS == 3
316 if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED)
317 /* This is the permanent pmd attached to the pgd; cannot
318 * free it */
319 return;
320 #endif
321 __pgd_val_set(*pgd, 0);
322 }
323 #else
324 /*
325 * The "pgd_xxx()" functions here are trivial for a folded two-level
326 * setup: the pgd is never bad, and a pmd always exists (as it's folded
327 * into the pgd entry)
328 */
pgd_none(pgd_t pgd)329 static inline int pgd_none(pgd_t pgd) { return 0; }
pgd_bad(pgd_t pgd)330 static inline int pgd_bad(pgd_t pgd) { return 0; }
pgd_present(pgd_t pgd)331 static inline int pgd_present(pgd_t pgd) { return 1; }
pgd_clear(pgd_t * pgdp)332 static inline void pgd_clear(pgd_t * pgdp) { }
333 #endif
334
335 /*
336 * The following only work if pte_present() is true.
337 * Undefined behaviour if not..
338 */
pte_dirty(pte_t pte)339 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
pte_young(pte_t pte)340 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
pte_write(pte_t pte)341 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
pte_file(pte_t pte)342 static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
pte_special(pte_t pte)343 static inline int pte_special(pte_t pte) { return 0; }
344
pte_mkclean(pte_t pte)345 static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
pte_mkold(pte_t pte)346 static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
pte_wrprotect(pte_t pte)347 static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; }
pte_mkdirty(pte_t pte)348 static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
pte_mkyoung(pte_t pte)349 static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
pte_mkwrite(pte_t pte)350 static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; }
pte_mkspecial(pte_t pte)351 static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
352
353 /*
354 * Conversion functions: convert a page and protection to a page entry,
355 * and a page entry and page directory to the page they refer to.
356 */
357 #define __mk_pte(addr,pgprot) \
358 ({ \
359 pte_t __pte; \
360 \
361 pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \
362 \
363 __pte; \
364 })
365
366 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
367
pfn_pte(unsigned long pfn,pgprot_t pgprot)368 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
369 {
370 pte_t pte;
371 pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot);
372 return pte;
373 }
374
pte_modify(pte_t pte,pgprot_t newprot)375 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
376 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
377
378 /* Permanent address of a page. On parisc we don't have highmem. */
379
380 #define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT)
381
382 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
383
384 #define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_address(pmd)))
385
386 #define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd)))
387 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
388
389 #define pgd_index(address) ((address) >> PGDIR_SHIFT)
390
391 /* to find an entry in a page-table-directory */
392 #define pgd_offset(mm, address) \
393 ((mm)->pgd + ((address) >> PGDIR_SHIFT))
394
395 /* to find an entry in a kernel page-table-directory */
396 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
397
398 /* Find an entry in the second-level page table.. */
399
400 #if PT_NLEVELS == 3
401 #define pmd_offset(dir,address) \
402 ((pmd_t *) pgd_page_vaddr(*(dir)) + (((address)>>PMD_SHIFT) & (PTRS_PER_PMD-1)))
403 #else
404 #define pmd_offset(dir,addr) ((pmd_t *) dir)
405 #endif
406
407 /* Find an entry in the third-level page table.. */
408 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
409 #define pte_offset_kernel(pmd, address) \
410 ((pte_t *) pmd_page_vaddr(*(pmd)) + pte_index(address))
411 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
412 #define pte_unmap(pte) do { } while (0)
413
414 #define pte_unmap(pte) do { } while (0)
415 #define pte_unmap_nested(pte) do { } while (0)
416
417 extern void paging_init (void);
418
419 /* Used for deferring calls to flush_dcache_page() */
420
421 #define PG_dcache_dirty PG_arch_1
422
423 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
424
425 /* Encode and de-code a swap entry */
426
427 #define __swp_type(x) ((x).val & 0x1f)
428 #define __swp_offset(x) ( (((x).val >> 6) & 0x7) | \
429 (((x).val >> 8) & ~0x7) )
430 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | \
431 ((offset & 0x7) << 6) | \
432 ((offset & ~0x7) << 8) })
433 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
434 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
435
ptep_test_and_clear_young(struct vm_area_struct * vma,unsigned long addr,pte_t * ptep)436 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
437 {
438 #ifdef CONFIG_SMP
439 if (!pte_young(*ptep))
440 return 0;
441 return test_and_clear_bit(xlate_pabit(_PAGE_ACCESSED_BIT), &pte_val(*ptep));
442 #else
443 pte_t pte = *ptep;
444 if (!pte_young(pte))
445 return 0;
446 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
447 return 1;
448 #endif
449 }
450
451 extern spinlock_t pa_dbit_lock;
452
453 struct mm_struct;
ptep_get_and_clear(struct mm_struct * mm,unsigned long addr,pte_t * ptep)454 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
455 {
456 pte_t old_pte;
457
458 spin_lock(&pa_dbit_lock);
459 old_pte = *ptep;
460 pte_clear(mm,addr,ptep);
461 spin_unlock(&pa_dbit_lock);
462
463 return old_pte;
464 }
465
ptep_set_wrprotect(struct mm_struct * mm,unsigned long addr,pte_t * ptep)466 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
467 {
468 #ifdef CONFIG_SMP
469 unsigned long new, old;
470
471 do {
472 old = pte_val(*ptep);
473 new = pte_val(pte_wrprotect(__pte (old)));
474 } while (cmpxchg((unsigned long *) ptep, old, new) != old);
475 purge_tlb_entries(mm, addr);
476 #else
477 pte_t old_pte = *ptep;
478 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
479 #endif
480 }
481
482 #define pte_same(A,B) (pte_val(A) == pte_val(B))
483
484 #endif /* !__ASSEMBLY__ */
485
486
487 /* TLB page size encoding - see table 3-1 in parisc20.pdf */
488 #define _PAGE_SIZE_ENCODING_4K 0
489 #define _PAGE_SIZE_ENCODING_16K 1
490 #define _PAGE_SIZE_ENCODING_64K 2
491 #define _PAGE_SIZE_ENCODING_256K 3
492 #define _PAGE_SIZE_ENCODING_1M 4
493 #define _PAGE_SIZE_ENCODING_4M 5
494 #define _PAGE_SIZE_ENCODING_16M 6
495 #define _PAGE_SIZE_ENCODING_64M 7
496
497 #if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
498 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K
499 #elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
500 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K
501 #elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
502 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K
503 #endif
504
505
506 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
507 remap_pfn_range(vma, vaddr, pfn, size, prot)
508
509 #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
510
511 /* We provide our own get_unmapped_area to provide cache coherency */
512
513 #define HAVE_ARCH_UNMAPPED_AREA
514
515 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
516 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
517 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
518 #define __HAVE_ARCH_PTE_SAME
519 #include <asm-generic/pgtable.h>
520
521 #endif /* _PARISC_PGTABLE_H */
522