1 /*
2 * SH7770 Setup
3 *
4 * Copyright (C) 2006 - 2008 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
14 #include <linux/sh_timer.h>
15 #include <linux/io.h>
16
17 static struct plat_sci_port scif0_platform_data = {
18 .mapbase = 0xff923000,
19 .flags = UPF_BOOT_AUTOCONF,
20 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
21 .scbrr_algo_id = SCBRR_ALGO_2,
22 .type = PORT_SCIF,
23 .irqs = { 61, 61, 61, 61 },
24 };
25
26 static struct platform_device scif0_device = {
27 .name = "sh-sci",
28 .id = 0,
29 .dev = {
30 .platform_data = &scif0_platform_data,
31 },
32 };
33
34 static struct plat_sci_port scif1_platform_data = {
35 .mapbase = 0xff924000,
36 .flags = UPF_BOOT_AUTOCONF,
37 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
38 .scbrr_algo_id = SCBRR_ALGO_2,
39 .type = PORT_SCIF,
40 .irqs = { 62, 62, 62, 62 },
41 };
42
43 static struct platform_device scif1_device = {
44 .name = "sh-sci",
45 .id = 1,
46 .dev = {
47 .platform_data = &scif1_platform_data,
48 },
49 };
50
51 static struct plat_sci_port scif2_platform_data = {
52 .mapbase = 0xff925000,
53 .flags = UPF_BOOT_AUTOCONF,
54 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
55 .scbrr_algo_id = SCBRR_ALGO_2,
56 .type = PORT_SCIF,
57 .irqs = { 63, 63, 63, 63 },
58 };
59
60 static struct platform_device scif2_device = {
61 .name = "sh-sci",
62 .id = 2,
63 .dev = {
64 .platform_data = &scif2_platform_data,
65 },
66 };
67
68 static struct plat_sci_port scif3_platform_data = {
69 .mapbase = 0xff926000,
70 .flags = UPF_BOOT_AUTOCONF,
71 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
72 .scbrr_algo_id = SCBRR_ALGO_2,
73 .type = PORT_SCIF,
74 .irqs = { 64, 64, 64, 64 },
75 };
76
77 static struct platform_device scif3_device = {
78 .name = "sh-sci",
79 .id = 3,
80 .dev = {
81 .platform_data = &scif3_platform_data,
82 },
83 };
84
85 static struct plat_sci_port scif4_platform_data = {
86 .mapbase = 0xff927000,
87 .flags = UPF_BOOT_AUTOCONF,
88 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
89 .scbrr_algo_id = SCBRR_ALGO_2,
90 .type = PORT_SCIF,
91 .irqs = { 65, 65, 65, 65 },
92 };
93
94 static struct platform_device scif4_device = {
95 .name = "sh-sci",
96 .id = 4,
97 .dev = {
98 .platform_data = &scif4_platform_data,
99 },
100 };
101
102 static struct plat_sci_port scif5_platform_data = {
103 .mapbase = 0xff928000,
104 .flags = UPF_BOOT_AUTOCONF,
105 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
106 .scbrr_algo_id = SCBRR_ALGO_2,
107 .type = PORT_SCIF,
108 .irqs = { 66, 66, 66, 66 },
109 };
110
111 static struct platform_device scif5_device = {
112 .name = "sh-sci",
113 .id = 5,
114 .dev = {
115 .platform_data = &scif5_platform_data,
116 },
117 };
118
119 static struct plat_sci_port scif6_platform_data = {
120 .mapbase = 0xff929000,
121 .flags = UPF_BOOT_AUTOCONF,
122 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
123 .scbrr_algo_id = SCBRR_ALGO_2,
124 .type = PORT_SCIF,
125 .irqs = { 67, 67, 67, 67 },
126 };
127
128 static struct platform_device scif6_device = {
129 .name = "sh-sci",
130 .id = 6,
131 .dev = {
132 .platform_data = &scif6_platform_data,
133 },
134 };
135
136 static struct plat_sci_port scif7_platform_data = {
137 .mapbase = 0xff92a000,
138 .flags = UPF_BOOT_AUTOCONF,
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
140 .scbrr_algo_id = SCBRR_ALGO_2,
141 .type = PORT_SCIF,
142 .irqs = { 68, 68, 68, 68 },
143 };
144
145 static struct platform_device scif7_device = {
146 .name = "sh-sci",
147 .id = 7,
148 .dev = {
149 .platform_data = &scif7_platform_data,
150 },
151 };
152
153 static struct plat_sci_port scif8_platform_data = {
154 .mapbase = 0xff92b000,
155 .flags = UPF_BOOT_AUTOCONF,
156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
157 .scbrr_algo_id = SCBRR_ALGO_2,
158 .type = PORT_SCIF,
159 .irqs = { 69, 69, 69, 69 },
160 };
161
162 static struct platform_device scif8_device = {
163 .name = "sh-sci",
164 .id = 8,
165 .dev = {
166 .platform_data = &scif8_platform_data,
167 },
168 };
169
170 static struct plat_sci_port scif9_platform_data = {
171 .mapbase = 0xff92c000,
172 .flags = UPF_BOOT_AUTOCONF,
173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
174 .scbrr_algo_id = SCBRR_ALGO_2,
175 .type = PORT_SCIF,
176 .irqs = { 70, 70, 70, 70 },
177 };
178
179 static struct platform_device scif9_device = {
180 .name = "sh-sci",
181 .id = 9,
182 .dev = {
183 .platform_data = &scif9_platform_data,
184 },
185 };
186
187 static struct sh_timer_config tmu0_platform_data = {
188 .channel_offset = 0x04,
189 .timer_bit = 0,
190 .clockevent_rating = 200,
191 };
192
193 static struct resource tmu0_resources[] = {
194 [0] = {
195 .start = 0xffd80008,
196 .end = 0xffd80013,
197 .flags = IORESOURCE_MEM,
198 },
199 [1] = {
200 .start = 16,
201 .flags = IORESOURCE_IRQ,
202 },
203 };
204
205 static struct platform_device tmu0_device = {
206 .name = "sh_tmu",
207 .id = 0,
208 .dev = {
209 .platform_data = &tmu0_platform_data,
210 },
211 .resource = tmu0_resources,
212 .num_resources = ARRAY_SIZE(tmu0_resources),
213 };
214
215 static struct sh_timer_config tmu1_platform_data = {
216 .channel_offset = 0x10,
217 .timer_bit = 1,
218 .clocksource_rating = 200,
219 };
220
221 static struct resource tmu1_resources[] = {
222 [0] = {
223 .start = 0xffd80014,
224 .end = 0xffd8001f,
225 .flags = IORESOURCE_MEM,
226 },
227 [1] = {
228 .start = 17,
229 .flags = IORESOURCE_IRQ,
230 },
231 };
232
233 static struct platform_device tmu1_device = {
234 .name = "sh_tmu",
235 .id = 1,
236 .dev = {
237 .platform_data = &tmu1_platform_data,
238 },
239 .resource = tmu1_resources,
240 .num_resources = ARRAY_SIZE(tmu1_resources),
241 };
242
243 static struct sh_timer_config tmu2_platform_data = {
244 .channel_offset = 0x1c,
245 .timer_bit = 2,
246 };
247
248 static struct resource tmu2_resources[] = {
249 [0] = {
250 .start = 0xffd80020,
251 .end = 0xffd8002f,
252 .flags = IORESOURCE_MEM,
253 },
254 [1] = {
255 .start = 18,
256 .flags = IORESOURCE_IRQ,
257 },
258 };
259
260 static struct platform_device tmu2_device = {
261 .name = "sh_tmu",
262 .id = 2,
263 .dev = {
264 .platform_data = &tmu2_platform_data,
265 },
266 .resource = tmu2_resources,
267 .num_resources = ARRAY_SIZE(tmu2_resources),
268 };
269
270 static struct sh_timer_config tmu3_platform_data = {
271 .channel_offset = 0x04,
272 .timer_bit = 0,
273 };
274
275 static struct resource tmu3_resources[] = {
276 [0] = {
277 .start = 0xffd81008,
278 .end = 0xffd81013,
279 .flags = IORESOURCE_MEM,
280 },
281 [1] = {
282 .start = 19,
283 .flags = IORESOURCE_IRQ,
284 },
285 };
286
287 static struct platform_device tmu3_device = {
288 .name = "sh_tmu",
289 .id = 3,
290 .dev = {
291 .platform_data = &tmu3_platform_data,
292 },
293 .resource = tmu3_resources,
294 .num_resources = ARRAY_SIZE(tmu3_resources),
295 };
296
297 static struct sh_timer_config tmu4_platform_data = {
298 .channel_offset = 0x10,
299 .timer_bit = 1,
300 };
301
302 static struct resource tmu4_resources[] = {
303 [0] = {
304 .start = 0xffd81014,
305 .end = 0xffd8101f,
306 .flags = IORESOURCE_MEM,
307 },
308 [1] = {
309 .start = 20,
310 .flags = IORESOURCE_IRQ,
311 },
312 };
313
314 static struct platform_device tmu4_device = {
315 .name = "sh_tmu",
316 .id = 4,
317 .dev = {
318 .platform_data = &tmu4_platform_data,
319 },
320 .resource = tmu4_resources,
321 .num_resources = ARRAY_SIZE(tmu4_resources),
322 };
323
324 static struct sh_timer_config tmu5_platform_data = {
325 .channel_offset = 0x1c,
326 .timer_bit = 2,
327 };
328
329 static struct resource tmu5_resources[] = {
330 [0] = {
331 .start = 0xffd81020,
332 .end = 0xffd8102f,
333 .flags = IORESOURCE_MEM,
334 },
335 [1] = {
336 .start = 21,
337 .flags = IORESOURCE_IRQ,
338 },
339 };
340
341 static struct platform_device tmu5_device = {
342 .name = "sh_tmu",
343 .id = 5,
344 .dev = {
345 .platform_data = &tmu5_platform_data,
346 },
347 .resource = tmu5_resources,
348 .num_resources = ARRAY_SIZE(tmu5_resources),
349 };
350
351 static struct sh_timer_config tmu6_platform_data = {
352 .channel_offset = 0x04,
353 .timer_bit = 0,
354 };
355
356 static struct resource tmu6_resources[] = {
357 [0] = {
358 .start = 0xffd82008,
359 .end = 0xffd82013,
360 .flags = IORESOURCE_MEM,
361 },
362 [1] = {
363 .start = 22,
364 .flags = IORESOURCE_IRQ,
365 },
366 };
367
368 static struct platform_device tmu6_device = {
369 .name = "sh_tmu",
370 .id = 6,
371 .dev = {
372 .platform_data = &tmu6_platform_data,
373 },
374 .resource = tmu6_resources,
375 .num_resources = ARRAY_SIZE(tmu6_resources),
376 };
377
378 static struct sh_timer_config tmu7_platform_data = {
379 .channel_offset = 0x10,
380 .timer_bit = 1,
381 };
382
383 static struct resource tmu7_resources[] = {
384 [0] = {
385 .start = 0xffd82014,
386 .end = 0xffd8201f,
387 .flags = IORESOURCE_MEM,
388 },
389 [1] = {
390 .start = 23,
391 .flags = IORESOURCE_IRQ,
392 },
393 };
394
395 static struct platform_device tmu7_device = {
396 .name = "sh_tmu",
397 .id = 7,
398 .dev = {
399 .platform_data = &tmu7_platform_data,
400 },
401 .resource = tmu7_resources,
402 .num_resources = ARRAY_SIZE(tmu7_resources),
403 };
404
405 static struct sh_timer_config tmu8_platform_data = {
406 .channel_offset = 0x1c,
407 .timer_bit = 2,
408 };
409
410 static struct resource tmu8_resources[] = {
411 [0] = {
412 .start = 0xffd82020,
413 .end = 0xffd8202b,
414 .flags = IORESOURCE_MEM,
415 },
416 [1] = {
417 .start = 24,
418 .flags = IORESOURCE_IRQ,
419 },
420 };
421
422 static struct platform_device tmu8_device = {
423 .name = "sh_tmu",
424 .id = 8,
425 .dev = {
426 .platform_data = &tmu8_platform_data,
427 },
428 .resource = tmu8_resources,
429 .num_resources = ARRAY_SIZE(tmu8_resources),
430 };
431
432 static struct platform_device *sh7770_devices[] __initdata = {
433 &scif0_device,
434 &scif1_device,
435 &scif2_device,
436 &scif3_device,
437 &scif4_device,
438 &scif5_device,
439 &scif6_device,
440 &scif7_device,
441 &scif8_device,
442 &scif9_device,
443 &tmu0_device,
444 &tmu1_device,
445 &tmu2_device,
446 &tmu3_device,
447 &tmu4_device,
448 &tmu5_device,
449 &tmu6_device,
450 &tmu7_device,
451 &tmu8_device,
452 };
453
sh7770_devices_setup(void)454 static int __init sh7770_devices_setup(void)
455 {
456 return platform_add_devices(sh7770_devices,
457 ARRAY_SIZE(sh7770_devices));
458 }
459 arch_initcall(sh7770_devices_setup);
460
461 static struct platform_device *sh7770_early_devices[] __initdata = {
462 &scif0_device,
463 &scif1_device,
464 &scif2_device,
465 &scif3_device,
466 &scif4_device,
467 &scif5_device,
468 &scif6_device,
469 &scif7_device,
470 &scif8_device,
471 &scif9_device,
472 &tmu0_device,
473 &tmu1_device,
474 &tmu2_device,
475 &tmu3_device,
476 &tmu4_device,
477 &tmu5_device,
478 &tmu6_device,
479 &tmu7_device,
480 &tmu8_device,
481 };
482
plat_early_device_setup(void)483 void __init plat_early_device_setup(void)
484 {
485 early_platform_add_devices(sh7770_early_devices,
486 ARRAY_SIZE(sh7770_early_devices));
487 }
488
489 enum {
490 UNUSED = 0,
491
492 /* interrupt sources */
493 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
494 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
495 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
496 IRL_HHLL, IRL_HHLH, IRL_HHHL,
497
498 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
499
500 GPIO,
501 TMU0, TMU1, TMU2, TMU2_TICPI,
502 TMU3, TMU4, TMU5, TMU5_TICPI,
503 TMU6, TMU7, TMU8,
504 HAC, IPI, SPDIF, HUDI, I2C,
505 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
506 I2S0, I2S1, I2S2, I2S3,
507 SRC_RX, SRC_TX, SRC_SPDIF,
508 DU, VIDEO_IN, REMOTE, YUV, USB, ATAPI, CAN, GPS, GFX2D,
509 GFX3D_MBX, GFX3D_DMAC,
510 EXBUS_ATA,
511 SPI0, SPI1,
512 SCIF089, SCIF1234, SCIF567,
513 ADC,
514 BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
515 BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
516 BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31,
517
518 /* interrupt groups */
519 TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC,
520 };
521
522 static struct intc_vect vectors[] __initdata = {
523 INTC_VECT(GPIO, 0x3e0),
524 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
525 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
526 INTC_VECT(TMU3, 0x480), INTC_VECT(TMU4, 0x4a0),
527 INTC_VECT(TMU5, 0x4c0), INTC_VECT(TMU5_TICPI, 0x4e0),
528 INTC_VECT(TMU6, 0x500), INTC_VECT(TMU7, 0x520),
529 INTC_VECT(TMU8, 0x540),
530 INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),
531 INTC_VECT(SPDIF, 0x5e0),
532 INTC_VECT(HUDI, 0x600), INTC_VECT(I2C, 0x620),
533 INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
534 INTC_VECT(DMAC0_DMINT2, 0x680),
535 INTC_VECT(I2S0, 0x6a0), INTC_VECT(I2S1, 0x6c0),
536 INTC_VECT(I2S2, 0x6e0), INTC_VECT(I2S3, 0x700),
537 INTC_VECT(SRC_RX, 0x720), INTC_VECT(SRC_TX, 0x740),
538 INTC_VECT(SRC_SPDIF, 0x760),
539 INTC_VECT(DU, 0x780), INTC_VECT(VIDEO_IN, 0x7a0),
540 INTC_VECT(REMOTE, 0x7c0), INTC_VECT(YUV, 0x7e0),
541 INTC_VECT(USB, 0x840), INTC_VECT(ATAPI, 0x860),
542 INTC_VECT(CAN, 0x880), INTC_VECT(GPS, 0x8a0),
543 INTC_VECT(GFX2D, 0x8c0),
544 INTC_VECT(GFX3D_MBX, 0x900), INTC_VECT(GFX3D_DMAC, 0x920),
545 INTC_VECT(EXBUS_ATA, 0x940),
546 INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980),
547 INTC_VECT(SCIF089, 0x9a0), INTC_VECT(SCIF1234, 0x9c0),
548 INTC_VECT(SCIF1234, 0x9e0), INTC_VECT(SCIF1234, 0xa00),
549 INTC_VECT(SCIF1234, 0xa20), INTC_VECT(SCIF567, 0xa40),
550 INTC_VECT(SCIF567, 0xa60), INTC_VECT(SCIF567, 0xa80),
551 INTC_VECT(SCIF089, 0xaa0), INTC_VECT(SCIF089, 0xac0),
552 INTC_VECT(ADC, 0xb20),
553 INTC_VECT(BBDMAC_0_3, 0xba0), INTC_VECT(BBDMAC_0_3, 0xbc0),
554 INTC_VECT(BBDMAC_0_3, 0xbe0), INTC_VECT(BBDMAC_0_3, 0xc00),
555 INTC_VECT(BBDMAC_4_7, 0xc20), INTC_VECT(BBDMAC_4_7, 0xc40),
556 INTC_VECT(BBDMAC_4_7, 0xc60), INTC_VECT(BBDMAC_4_7, 0xc80),
557 INTC_VECT(BBDMAC_8_10, 0xca0), INTC_VECT(BBDMAC_8_10, 0xcc0),
558 INTC_VECT(BBDMAC_8_10, 0xce0), INTC_VECT(BBDMAC_11_14, 0xd00),
559 INTC_VECT(BBDMAC_11_14, 0xd20), INTC_VECT(BBDMAC_11_14, 0xd40),
560 INTC_VECT(BBDMAC_11_14, 0xd60), INTC_VECT(BBDMAC_15_18, 0xd80),
561 INTC_VECT(BBDMAC_15_18, 0xda0), INTC_VECT(BBDMAC_15_18, 0xdc0),
562 INTC_VECT(BBDMAC_15_18, 0xde0), INTC_VECT(BBDMAC_19_22, 0xe00),
563 INTC_VECT(BBDMAC_19_22, 0xe20), INTC_VECT(BBDMAC_19_22, 0xe40),
564 INTC_VECT(BBDMAC_19_22, 0xe60), INTC_VECT(BBDMAC_23_26, 0xe80),
565 INTC_VECT(BBDMAC_23_26, 0xea0), INTC_VECT(BBDMAC_23_26, 0xec0),
566 INTC_VECT(BBDMAC_23_26, 0xee0), INTC_VECT(BBDMAC_27, 0xf00),
567 INTC_VECT(BBDMAC_28, 0xf20), INTC_VECT(BBDMAC_29, 0xf40),
568 INTC_VECT(BBDMAC_30, 0xf60), INTC_VECT(BBDMAC_31, 0xf80),
569 };
570
571 static struct intc_group groups[] __initdata = {
572 INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
573 TMU5_TICPI, TMU6, TMU7, TMU8),
574 INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2),
575 INTC_GROUP(I2S, I2S0, I2S1, I2S2, I2S3),
576 INTC_GROUP(SRC, SRC_RX, SRC_TX, SRC_SPDIF),
577 INTC_GROUP(GFX3D, GFX3D_MBX, GFX3D_DMAC),
578 INTC_GROUP(SPI, SPI0, SPI1),
579 INTC_GROUP(SCIF, SCIF089, SCIF1234, SCIF567),
580 INTC_GROUP(BBDMAC,
581 BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
582 BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
583 BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31),
584 };
585
586 static struct intc_mask_reg mask_registers[] __initdata = {
587 { 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */
588 { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D,
589 GPS, CAN, ATAPI, USB, YUV, REMOTE, VIDEO_IN, DU, SRC, I2S,
590 DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },
591 };
592
593 static struct intc_prio_reg prio_registers[] __initdata = {
594 { 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } },
595 { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
596 { 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC, I2S, SRC, DU } },
597 { 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN, REMOTE, YUV, USB } },
598 { 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI, CAN, GPS, GFX2D } },
599 { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } },
600 { 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234, SCIF567, SCIF089 } },
601 { 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC, 0, 0, BBDMAC_0_3 } },
602 { 0xffe00020, 0, 32, 8, /* INT2PRI8 */
603 { BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, BBDMAC_15_18 } },
604 { 0xffe00024, 0, 32, 8, /* INT2PRI9 */
605 { BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, BBDMAC_28 } },
606 { 0xffe00028, 0, 32, 8, /* INT2PRI10 */
607 { BBDMAC_29, BBDMAC_30, BBDMAC_31 } },
608 { 0xffe0002c, 0, 32, 8, /* INT2PRI11 */
609 { TMU1, TMU2, TMU2_TICPI, TMU3 } },
610 { 0xffe00030, 0, 32, 8, /* INT2PRI12 */
611 { TMU4, TMU5, TMU5_TICPI, TMU6 } },
612 { 0xffe00034, 0, 32, 8, /* INT2PRI13 */
613 { TMU7, TMU8 } },
614 };
615
616 static DECLARE_INTC_DESC(intc_desc, "sh7770", vectors, groups,
617 mask_registers, prio_registers, NULL);
618
619 /* Support for external interrupt pins in IRQ mode */
620 static struct intc_vect irq_vectors[] __initdata = {
621 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
622 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
623 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
624 };
625
626 static struct intc_mask_reg irq_mask_registers[] __initdata = {
627 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
628 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, } },
629 };
630
631 static struct intc_prio_reg irq_prio_registers[] __initdata = {
632 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
633 IRQ4, IRQ5, } },
634 };
635
636 static struct intc_sense_reg irq_sense_registers[] __initdata = {
637 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
638 IRQ4, IRQ5, } },
639 };
640
641 static DECLARE_INTC_DESC(intc_irq_desc, "sh7770-irq", irq_vectors,
642 NULL, irq_mask_registers, irq_prio_registers,
643 irq_sense_registers);
644
645 /* External interrupt pins in IRL mode */
646 static struct intc_vect irl_vectors[] __initdata = {
647 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
648 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
649 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
650 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
651 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
652 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
653 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
654 INTC_VECT(IRL_HHHL, 0x3c0),
655 };
656
657 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
658 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
659 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
660 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
661 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
662 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
663 };
664
665 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
666 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
667 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
668 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
669 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
670 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
671 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
672 };
673
674 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
675 NULL, irl7654_mask_registers, NULL, NULL);
676
677 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
678 NULL, irl3210_mask_registers, NULL, NULL);
679
680 #define INTC_ICR0 0xffd00000
681 #define INTC_INTMSK0 0xffd00044
682 #define INTC_INTMSK1 0xffd00048
683 #define INTC_INTMSK2 0xffd40080
684 #define INTC_INTMSKCLR1 0xffd00068
685 #define INTC_INTMSKCLR2 0xffd40084
686
plat_irq_setup(void)687 void __init plat_irq_setup(void)
688 {
689 /* disable IRQ7-0 */
690 __raw_writel(0xff000000, INTC_INTMSK0);
691
692 /* disable IRL3-0 + IRL7-4 */
693 __raw_writel(0xc0000000, INTC_INTMSK1);
694 __raw_writel(0xfffefffe, INTC_INTMSK2);
695
696 /* select IRL mode for IRL3-0 + IRL7-4 */
697 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
698
699 /* disable holding function, ie enable "SH-4 Mode" */
700 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
701
702 register_intc_controller(&intc_desc);
703 }
704
plat_irq_setup_pins(int mode)705 void __init plat_irq_setup_pins(int mode)
706 {
707 switch (mode) {
708 case IRQ_MODE_IRQ:
709 /* select IRQ mode for IRL3-0 + IRL7-4 */
710 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
711 register_intc_controller(&intc_irq_desc);
712 break;
713 case IRQ_MODE_IRL7654:
714 /* enable IRL7-4 but don't provide any masking */
715 __raw_writel(0x40000000, INTC_INTMSKCLR1);
716 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
717 break;
718 case IRQ_MODE_IRL3210:
719 /* enable IRL0-3 but don't provide any masking */
720 __raw_writel(0x80000000, INTC_INTMSKCLR1);
721 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
722 break;
723 case IRQ_MODE_IRL7654_MASK:
724 /* enable IRL7-4 and mask using cpu intc controller */
725 __raw_writel(0x40000000, INTC_INTMSKCLR1);
726 register_intc_controller(&intc_irl7654_desc);
727 break;
728 case IRQ_MODE_IRL3210_MASK:
729 /* enable IRL0-3 and mask using cpu intc controller */
730 __raw_writel(0x80000000, INTC_INTMSKCLR1);
731 register_intc_controller(&intc_irl3210_desc);
732 break;
733 default:
734 BUG();
735 }
736 }
737