115 typedef struct ia64_sal_retval (*ia64_sal_handler) (u64, ...);
170 	u64 pal_proc;
171 	u64 sal_proc;
172 	u64 gp;
185 	u64 addr;		/* physical address of memory */
202 	u64 addr;		/* virtual address of area covered */
203 	u64 page_size;		/* encoded page size */
211 	u64 domain_info;	/* physical address of domain info table */
215 	u64 proc_count;		/* number of processors in domain */
216 	u64 proc_list;		/* physical address of LID array */
220 	u64 id  : 8;		/* id of processor */
221 	u64 eid : 8;		/* eid of processor */
231 	u64 vector;		/* interrupt vector in range 0x10-0xff */
327 	u64 id;				/* Unique monotonically increasing ID */
363 		u64 check_info              : 1,
370 	u64 check_info;
371 	u64 requestor_identifier;
372 	u64 responder_identifier;
373 	u64 target_identifier;
374 	u64 precise_ip;
379 		u64 minstate        : 1,
388 	u64 br[8];
389 	u64 cr[128];
390 	u64 ar[128];
391 	u64 rr[8];
396 	u64 regs[5];
397 	u64 reserved;
403 		u64 proc_error_map      : 1,
415 	u64 proc_error_map;
416 	u64 proc_state_parameter;
417 	u64 proc_cr_lid;
451 		u64 error_status    : 1,
470 	u64 error_status;
471 	u64 physical_addr;
472 	u64 addr_mask;
481 	u64 requestor_id;
482 	u64 responder_id;
483 	u64 target_id;
484 	u64 bus_spec_data;
492 		u64 record_id       : 1,
520 		u64 err_status      : 1,
532 	u64 err_status;
536 	u64 bus_address;
537 	u64 bus_data;
538 	u64 bus_cmd;
539 	u64 requestor_id;
540 	u64 responder_id;
541 	u64 target_id;
548 		u64 event_type      : 1,
563 		u64 err_status      : 1,
571 	u64 err_status;
584 	u64 reg_data_pairs[1];
596 		u64 err_status      : 1,
601 	u64 err_status;
609 		u64 err_status      : 1,
617 	u64 err_status;
618 	u64 requestor_id;
619 	u64 responder_id;
620 	u64 target_id;
621 	u64 bus_spec_data;
628 		u64 err_status      : 1,
636 	u64 err_status;
637 	u64 requestor_id;
638 	u64 responder_id;
639 	u64 target_id;
640 	u64 bus_spec_data;
669 extern s64 ia64_sal_cache_flush (u64 cache_type);
686 ia64_sal_clear_state_info (u64 sal_info_type)  in ia64_sal_clear_state_info()
698 static inline u64
699 ia64_sal_get_state_info (u64 sal_info_type, u64 *sal_info)  in ia64_sal_get_state_info()
714 static inline u64
715 ia64_sal_get_state_info_size (u64 sal_info_type)  in ia64_sal_get_state_info_size()
746 ia64_sal_mc_set_params (u64 param_type, u64 i_or_m, u64 i_or_m_val, u64 timeout, u64 rz_always)  in ia64_sal_mc_set_params()
756 ia64_sal_pci_config_read (u64 pci_config_addr, int type, u64 size, u64 *value)  in ia64_sal_pci_config_read()
767 ia64_sal_pci_config_write (u64 pci_config_addr, int type, u64 size, u64 value)  in ia64_sal_pci_config_write()
780 ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr)  in ia64_sal_register_physical_addr()
794 ia64_sal_set_vectors (u64 vector_type,  in ia64_sal_set_vectors()
795 		      u64 handler_addr1, u64 gp1, u64 handler_len1,  in ia64_sal_set_vectors()
796 		      u64 handler_addr2, u64 gp2, u64 handler_len2)  in ia64_sal_set_vectors()
808 ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,  in ia64_sal_update_pal()
809 		     u64 *error_code, u64 *scratch_buf_size_needed)  in ia64_sal_update_pal()
838 extern int (*salinfo_platform_oemdata)(const u8 *, u8 **, u64 *);
847 extern int ia64_sal_oemcall(struct ia64_sal_retval *, u64, u64, u64, u64, u64,
848 			    u64, u64, u64);
849 extern int ia64_sal_oemcall_nolock(struct ia64_sal_retval *, u64, u64, u64,
850 				   u64, u64, u64, u64, u64);
851 extern int ia64_sal_oemcall_reentrant(struct ia64_sal_retval *, u64, u64, u64,
852 				      u64, u64, u64, u64, u64);
864 	u64 rr[8];		/* Region Registers */
865 	u64 br[6];		/* br0:
867 	u64 gr1;		/* SAL:GP */
868 	u64 gr12;		/* SAL:SP */
869 	u64 gr13;		/* SAL: Task Pointer */
870 	u64 fpsr;
871 	u64 pfs;
872 	u64 rnat;
873 	u64 unat;
874 	u64 bspstore;
875 	u64 dcr;		/* Default Control Register */
876 	u64 iva;
877 	u64 pta;
878 	u64 itv;
879 	u64 pmv;
880 	u64 cmcv;
881 	u64 lrr[2];
882 	u64 gr[4];
883 	u64 pr;			/* Predicate registers */
884 	u64 lc;			/* Loop Count */