Lines Matching refs:r22

126 	shr.u r22=r21,3
134 (p8)	shr r22=r22,r27
138 	shr.u r18=r22,PGDIR_SHIFT		// get bottom portion of pgd index bit
153 	shr.u r28=r22,PUD_SHIFT			// shift pud index into position
155 	shr.u r18=r22,PMD_SHIFT			// shift pmd index into position
164 	shr.u r18=r22,PMD_SHIFT			// shift pmd index into position
174 	shr.u r19=r22,PAGE_SHIFT		// shift pte index into position
183 	MOV_FROM_IHA(r22)			// get the VHPT address that caused the TLB miss
191 	MOV_TO_IFA(r22, r24)
239 (p6)	ptc.l r22,r27				// purge PTE page translation
349 	shr.u r22=r16,61			// get the region number into r21
351 	cmp.gt p8,p0=6,r22			// user mode
389 	shr.u r22=r16,61			// get the region number into r21
391 	cmp.gt p8,p0=6,r22			// access to region 0-5
409 	and r22=IA64_ISR_CODE_MASK,r20		// get the isr.code field
416 (p9)	cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22	// check isr.code field
465 	add r22=-PAGE_SHIFT,r18			// adjustment for hugetlb address
468 	shr.u r22=r16,r22
483 	shr.u r18=r22,PUD_SHIFT			// shift pud index into position
485 	shr.u r18=r22,PMD_SHIFT			// shift pmd index into position
495 	shr.u r18=r22,PMD_SHIFT			// shift pmd index into position
502 	shr.u r19=r22,PAGE_SHIFT		// shift pte index into position
773 	addl r22=IA64_RBS_OFFSET,r1		// A    compute base of RBS
777 	lfetch.fault.excl.nt1 [r22]		// M0|1 prefetch RBS
781 	mov.m ar.bspstore=r22			// M2   switch to kernel RBS
834 	sub r22=r19,r18				// A  stime before leave
839 	add r20=r20,r22				// A  sum stime
979 (pUStk) sub r18=r18,r22				// r18=RSE.ndirty*8
1067 	sub r22=r19,r18				// stime before leave kernel
1072 	add r23=r23,r22				// sum stime