Lines Matching refs:u32
48 u32 id; /* 0x0: Identification register */
49 u32 hwgen; /* 0x4: General HW params */
50 u32 hwhost; /* 0x8: Host HW params */
51 u32 hwdev; /* 0xc: Device HW params */
52 u32 hwtxbuf; /* 0x10: Tx buffer HW params */
53 u32 hwrxbuf; /* 0x14: Rx buffer HW params */
54 u32 reserved[26];
55 u32 timer0_load; /* 0x80: General-purpose timer 0 load*/
56 u32 timer0_ctrl; /* 0x84: General-purpose timer 0 control */
57 u32 timer1_load; /* 0x88: General-purpose timer 1 load*/
58 u32 timer1_ctrl; /* 0x8c: General-purpose timer 1 control */
63 u32 isr; /* 0x0: Interrupt status */
64 u32 imr; /* 0x4: Interrupt mask */
65 u32 thcr0; /* 0x8: Transaction header capture 0 */
66 u32 thcr1; /* 0xc: Transaction header capture 1 */
67 u32 int_stat; /* 0x10: Interrupt status summary */
68 u32 phy_cfg; /* 0x14: USB phy config */
73 u32 hciver; /* 0x0: Version and offset to operational regs */
74 u32 hcsparams; /* 0x4: Host control structural parameters */
75 u32 hccparams; /* 0x8: Host control capability parameters */
76 u32 reserved0[5];
77 u32 dciver; /* 0x20: Device interface version */
78 u32 dccparams; /* 0x24: Device control capability parameters */
79 u32 reserved1[6];
80 u32 cmd; /* 0x40: USB command */
81 u32 sts; /* 0x44: USB status */
82 u32 int_ena; /* 0x48: USB interrupt enable */
83 u32 frindex; /* 0x4c: Frame index */
84 u32 reserved3;
87 u32 flb_addr; /* 0x54: Frame list base address */
88 u32 next_async_addr; /* 0x58: next asynchronous addr */
89 u32 ttctrl; /* 0x5c: embedded transaction translator
91 u32 burst_size; /* 0x60: Controller burst size */
92 u32 tx_fifo_ctrl; /* 0x64: Tx latency FIFO tuning */
93 u32 reserved0[4];
94 u32 endpt_nak; /* 0x78: Endpoint NAK */
95 u32 endpt_nak_ena; /* 0x7c: Endpoint NAK enable */
96 u32 cfg_flag; /* 0x80: Config flag */
97 u32 port_sc1; /* 0x84: Port status & control 1 */
98 u32 reserved1[7];
99 u32 otgsc; /* 0xa4: OTG status & control */
100 u32 mode; /* 0xa8: USB controller mode */
104 u32 dev_addr; /* 0x54: Device address */
105 u32 endpt_list_addr; /* 0x58: Endpoint list address */
106 u32 reserved0[7];
107 u32 endpt_nak; /* 0x74 */
108 u32 endpt_nak_ctrl; /* 0x78 */
109 u32 cfg_flag; /* 0x80 */
110 u32 port_sc1; /* 0x84: Port status & control 1 */
111 u32 reserved[7];
112 u32 otgsc; /* 0xa4: OTG status & control */
113 u32 mode; /* 0xa8: USB controller mode */
114 u32 endpt_setup_stat; /* 0xac */
115 u32 endpt_prime; /* 0xb0 */
116 u32 endpt_flush; /* 0xb4 */
117 u32 endpt_stat; /* 0xb8 */
118 u32 endpt_complete; /* 0xbc */
119 u32 endpt_ctrl0; /* 0xc0 */
120 u32 endpt_ctrl1; /* 0xc4 */
121 u32 endpt_ctrl2; /* 0xc8 */
122 u32 endpt_ctrl3; /* 0xcc */