Lines Matching refs:_SB_MAKEMASK1
224 #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3)
225 #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4)
226 #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5)
227 #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6)
234 #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12)
235 #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13)
236 #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14)
237 #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15)
238 #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
249 #define M_SYS_PCI_HOST _SB_MAKEMASK1(19)
250 #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20)
251 #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21)
252 #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)
253 #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23)
254 #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24)
255 #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25)
264 #define M_SYS_CLKSTOP _SB_MAKEMASK1(32)
265 #define M_SYS_CLKSTEP _SB_MAKEMASK1(33)
272 #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42)
283 #define M_SYS_MEM_RESET _SB_MAKEMASK1(49)
284 #define M_SYS_L2C_RESET _SB_MAKEMASK1(50)
285 #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51)
286 #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52)
287 #define M_SYS_SCD_RESET _SB_MAKEMASK1(53)
291 #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54)
292 #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55)
294 #define M_SYS_UNICPU0 _SB_MAKEMASK1(56)
295 #define M_SYS_UNICPU1 _SB_MAKEMASK1(57)
297 #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58)
298 #define M_SYS_EXT_RESET _SB_MAKEMASK1(59)
299 #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60)
301 #define M_SYS_MISR_MODE _SB_MAKEMASK1(61)
302 #define M_SYS_MISR_RESET _SB_MAKEMASK1(62)
305 #define M_SYS_SW_FLAG _SB_MAKEMASK1(63)
339 #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
355 #define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
376 #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0)
377 #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1)
405 #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
406 #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
429 #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30)
481 #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
482 #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
483 #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5)
484 #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6)
485 #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
520 #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
521 #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
522 #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
523 #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3)
524 #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4)
525 #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
526 #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
527 #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
529 #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8)
557 #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4)
558 #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5)
559 #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6)
560 #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7)
561 #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9)
562 #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10)
563 #define M_SCD_TREVT_READ _SB_MAKEMASK1(11)
646 #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18)
647 #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19)
648 #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20)
649 #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21)
650 #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22)
651 #define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23)
652 #define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24)