Lines Matching refs:__MASK
63 #define __MASK(X) (1<<(X))
65 #define __MASK(X) (1UL<<(X)) macro
69 #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
70 #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
71 #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
87 #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
88 #define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */
89 #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
90 #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */
91 #define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */
92 #define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */
93 #define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */
94 #define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */
95 #define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */
96 #define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */
97 #define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */
98 #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
99 #define MSR_SE __MASK(MSR_SE_LG) /* Single Step */
100 #define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */
101 #define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */
102 #define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */
103 #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
104 #define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */
105 #define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */
106 #define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */
107 #define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */
109 #define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */
111 #define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
112 #define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
114 #define MSR_TM __MASK(MSR_TM_LG) /* Transactional Mem Available */
116 #define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */
117 #define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */
240 #define TEXASR_FS __MASK(63-36) /* TEXASR Failure Summary */
258 #define DAWRX_USER __MASK(0)
259 #define DAWRX_KERNEL __MASK(1)
260 #define DAWRX_HYP __MASK(2)
261 #define DAWRX_WTI __MASK(3)
262 #define DAWRX_WT __MASK(4)
263 #define DAWRX_DR __MASK(5)
264 #define DAWRX_DW __MASK(6)
268 #define DABRX_USER __MASK(0)
269 #define DABRX_KERNEL __MASK(1)
270 #define DABRX_HYP __MASK(2)
271 #define DABRX_BTI __MASK(3)
375 #define FSCR_SCV __MASK(FSCR_SCV_LG)
376 #define FSCR_TAR __MASK(FSCR_TAR_LG)
377 #define FSCR_EBB __MASK(FSCR_EBB_LG)
378 #define FSCR_DSCR __MASK(FSCR_DSCR_LG)
380 #define HFSCR_MSGP __MASK(FSCR_MSGP_LG)
381 #define HFSCR_TAR __MASK(FSCR_TAR_LG)
382 #define HFSCR_EBB __MASK(FSCR_EBB_LG)
383 #define HFSCR_TM __MASK(FSCR_TM_LG)
384 #define HFSCR_PM __MASK(FSCR_PM_LG)
385 #define HFSCR_BHRB __MASK(FSCR_BHRB_LG)
386 #define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
387 #define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
388 #define HFSCR_FP __MASK(FSCR_FP_LG)
539 #define HID0_POWER8_4LPARMODE __MASK(61)
540 #define HID0_POWER8_2LPARMODE __MASK(57)
541 #define HID0_POWER8_1TO2LPAR __MASK(52)
542 #define HID0_POWER8_1TO4LPAR __MASK(51)
543 #define HID0_POWER8_DYNLPARDIS __MASK(48)
546 #define HID0_POWER9_RADIX __MASK(63 - 8)