Lines Matching refs:u32

51 	u32	ctl;		/* 0x000 - L2 control */
53 	u32	ewar0;		/* 0x010 - External write address 0 */
54 	u32	ewarea0;	/* 0x014 - External write address extended 0 */
55 	u32	ewcr0;		/* 0x018 - External write ctrl */
57 	u32	ewar1;		/* 0x020 - External write address 1 */
58 	u32	ewarea1;	/* 0x024 - External write address extended 1 */
59 	u32	ewcr1;		/* 0x028 - External write ctrl 1 */
61 	u32	ewar2;		/* 0x030 - External write address 2 */
62 	u32	ewarea2;	/* 0x034 - External write address extended 2 */
63 	u32	ewcr2;		/* 0x038 - External write ctrl 2 */
65 	u32	ewar3;		/* 0x040 - External write address 3 */
66 	u32	ewarea3;	/* 0x044 - External write address extended 3 */
67 	u32	ewcr3;		/* 0x048 - External write ctrl 3 */
69 	u32	srbar0;		/* 0x100 - SRAM base address 0 */
70 	u32	srbarea0;	/* 0x104 - SRAM base addr reg ext address 0 */
71 	u32	srbar1;		/* 0x108 - SRAM base address 1 */
72 	u32	srbarea1;	/* 0x10C - SRAM base addr reg ext address 1 */
74 	u32	errinjhi;	/* 0xE00 - Error injection mask high */
75 	u32	errinjlo;	/* 0xE04 - Error injection mask low */
76 	u32	errinjctl;	/* 0xE08 - Error injection tag/ecc control */
78 	u32	captdatahi;	/* 0xE20 - Error data high capture */
79 	u32	captdatalo;	/* 0xE24 - Error data low capture */
80 	u32	captecc;	/* 0xE28 - Error syndrome */
82 	u32	errdet;		/* 0xE40 - Error detect */
83 	u32	errdis;		/* 0xE44 - Error disable */
84 	u32	errinten;	/* 0xE48 - Error interrupt enable */
85 	u32	errattr;	/* 0xE4c - Error attribute capture */
86 	u32	erradrrl;	/* 0xE50 - Error address capture low */
87 	u32	erradrrh;	/* 0xE54 - Error address capture high */
88 	u32	errctl;		/* 0xE58 - Error control */