34 	unsigned int mask = 1 << hw_cpu;  in rcpm_v1_irq_mask()  local
36 	setbits32(&rcpm_v1_regs->cpmimr, mask);  in rcpm_v1_irq_mask()
37 	setbits32(&rcpm_v1_regs->cpmcimr, mask);  in rcpm_v1_irq_mask()
38 	setbits32(&rcpm_v1_regs->cpmmcmr, mask);  in rcpm_v1_irq_mask()
39 	setbits32(&rcpm_v1_regs->cpmnmimr, mask);  in rcpm_v1_irq_mask()
45 	unsigned int mask = 1 << hw_cpu;  in rcpm_v2_irq_mask()  local
47 	setbits32(&rcpm_v2_regs->tpmimr0, mask);  in rcpm_v2_irq_mask()
48 	setbits32(&rcpm_v2_regs->tpmcimr0, mask);  in rcpm_v2_irq_mask()
49 	setbits32(&rcpm_v2_regs->tpmmcmr0, mask);  in rcpm_v2_irq_mask()
50 	setbits32(&rcpm_v2_regs->tpmnmimr0, mask);  in rcpm_v2_irq_mask()
56 	unsigned int mask = 1 << hw_cpu;  in rcpm_v1_irq_unmask()  local
58 	clrbits32(&rcpm_v1_regs->cpmimr, mask);  in rcpm_v1_irq_unmask()
59 	clrbits32(&rcpm_v1_regs->cpmcimr, mask);  in rcpm_v1_irq_unmask()
60 	clrbits32(&rcpm_v1_regs->cpmmcmr, mask);  in rcpm_v1_irq_unmask()
61 	clrbits32(&rcpm_v1_regs->cpmnmimr, mask);  in rcpm_v1_irq_unmask()
67 	unsigned int mask = 1 << hw_cpu;  in rcpm_v2_irq_unmask()  local
69 	clrbits32(&rcpm_v2_regs->tpmimr0, mask);  in rcpm_v2_irq_unmask()
70 	clrbits32(&rcpm_v2_regs->tpmcimr0, mask);  in rcpm_v2_irq_unmask()
71 	clrbits32(&rcpm_v2_regs->tpmmcmr0, mask);  in rcpm_v2_irq_unmask()
72 	clrbits32(&rcpm_v2_regs->tpmnmimr0, mask);  in rcpm_v2_irq_unmask()
75 static void rcpm_v1_set_ip_power(bool enable, u32 mask)  in rcpm_v1_set_ip_power()  argument
78 		setbits32(&rcpm_v1_regs->ippdexpcr, mask);  in rcpm_v1_set_ip_power()
80 		clrbits32(&rcpm_v1_regs->ippdexpcr, mask);  in rcpm_v1_set_ip_power()
83 static void rcpm_v2_set_ip_power(bool enable, u32 mask)  in rcpm_v2_set_ip_power()  argument
86 		setbits32(&rcpm_v2_regs->ippdexpcr[0], mask);  in rcpm_v2_set_ip_power()
88 		clrbits32(&rcpm_v2_regs->ippdexpcr[0], mask);  in rcpm_v2_set_ip_power()
94 	unsigned int mask = 1 << hw_cpu;  in rcpm_v1_cpu_enter_state()  local
98 		setbits32(&rcpm_v1_regs->cdozcr, mask);  in rcpm_v1_cpu_enter_state()
101 		setbits32(&rcpm_v1_regs->cnapcr, mask);  in rcpm_v1_cpu_enter_state()
112 	u32 mask = 1 << cpu_core_index_of_thread(cpu);  in rcpm_v2_cpu_enter_state()  local
120 		setbits32(&rcpm_v2_regs->pcph15setr, mask);  in rcpm_v2_cpu_enter_state()
123 		setbits32(&rcpm_v2_regs->pcph20setr, mask);  in rcpm_v2_cpu_enter_state()
126 		setbits32(&rcpm_v2_regs->pcph30setr, mask);  in rcpm_v2_cpu_enter_state()
171 	unsigned int mask = 1 << hw_cpu;  in rcpm_v1_cpu_exit_state()  local
175 		clrbits32(&rcpm_v1_regs->cdozcr, mask);  in rcpm_v1_cpu_exit_state()
178 		clrbits32(&rcpm_v1_regs->cnapcr, mask);  in rcpm_v1_cpu_exit_state()
195 	u32 mask = 1 << cpu_core_index_of_thread(cpu);  in rcpm_v2_cpu_exit_state()  local
202 		setbits32(&rcpm_v2_regs->pcph15clrr, mask);  in rcpm_v2_cpu_exit_state()
205 		setbits32(&rcpm_v2_regs->pcph20clrr, mask);  in rcpm_v2_cpu_exit_state()
208 		setbits32(&rcpm_v2_regs->pcph30clrr, mask);  in rcpm_v2_cpu_exit_state()
290 	static u32 mask;  in rcpm_common_freeze_time_base()  local
293 		mask = in_be32(tben_reg);  in rcpm_common_freeze_time_base()
294 		clrbits32(tben_reg, mask);  in rcpm_common_freeze_time_base()
296 		setbits32(tben_reg, mask);  in rcpm_common_freeze_time_base()