Lines Matching refs:readl
156 if (readl(PM_PLLVGACFG) == pll_vgacfg) in clk_set_rate()
163 while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_VGADFC) in clk_set_rate()
168 writel(readl(PM_PCGR) | PM_PCGR_VGACLK, PM_PCGR); in clk_set_rate()
170 writel((readl(PM_DIVCFG) & ~PM_DIVCFG_VGACLK_MASK) in clk_set_rate()
173 writel(readl(PM_SWRESET) | PM_SWRESET_VGADIV, PM_SWRESET); in clk_set_rate()
174 while ((readl(PM_SWRESET) & PM_SWRESET_VGADIV) in clk_set_rate()
178 writel(readl(PM_PCGR) & ~PM_PCGR_VGACLK, PM_PCGR); in clk_set_rate()
182 u32 pll_rate, divstatus = readl(PM_DIVSTATUS); in clk_set_rate()
207 while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_SYSDFC) in clk_set_rate()
328 u32 pllrate, divstatus = readl(PM_DIVSTATUS); in clk_init()
329 u32 pcgr_val = readl(PM_PCGR); in clk_init()
336 pllrate = readl(PM_PLLSYSSTATUS); in clk_init()
351 pllrate = readl(PM_PLLDDRSTATUS); in clk_init()
362 pllrate = readl(PM_PLLVGASTATUS); in clk_init()