Lines Matching refs:bank
120 static enum smca_bank_types smca_get_bank_type(unsigned int bank) in smca_get_bank_type() argument
124 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
127 b = &smca_banks[bank]; in smca_get_bank_type()
193 static void smca_configure(unsigned int bank, unsigned int cpu) in smca_configure() argument
198 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); in smca_configure()
231 if (smca_banks[bank].hwid && smca_banks[bank].hwid->hwid_mcatype != 0) in smca_configure()
234 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { in smca_configure()
235 pr_warn("Failed to read MCA_IPID for bank %d\n", bank); in smca_configure()
245 smca_banks[bank].hwid = s_hwid; in smca_configure()
246 smca_banks[bank].id = low; in smca_configure()
247 smca_banks[bank].sysfs_id = s_hwid->count++; in smca_configure()
261 static inline bool is_shared_bank(int bank) in is_shared_bank() argument
271 return (bank == 4); in is_shared_bank()
294 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) in lvt_interrupt_supported() argument
299 if (bank == 4) in lvt_interrupt_supported()
316 b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
331 b->cpu, apic, b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
438 static u32 smca_get_block_address(unsigned int cpu, unsigned int bank, in smca_get_block_address() argument
444 if (smca_get_bank_type(bank) == SMCA_RESERVED) in smca_get_block_address()
448 return MSR_AMD64_SMCA_MCx_MISC(bank); in smca_get_block_address()
451 if (smca_bank_addrs[bank][block] != -1) in smca_get_block_address()
452 return smca_bank_addrs[bank][block]; in smca_get_block_address()
458 if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) in smca_get_block_address()
464 if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && in smca_get_block_address()
466 addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); in smca_get_block_address()
469 smca_bank_addrs[bank][block] = addr; in smca_get_block_address()
474 unsigned int bank, unsigned int block) in get_block_address() argument
478 if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) in get_block_address()
482 return smca_get_block_address(cpu, bank, block); in get_block_address()
487 addr = msr_ops.misc(bank); in get_block_address()
501 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, in prepare_threshold_block() argument
510 per_cpu(bank_map, cpu) |= (1 << bank); in prepare_threshold_block()
514 b.bank = bank; in prepare_threshold_block()
517 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); in prepare_threshold_block()
585 unsigned int bank, block, cpu = smp_processor_id(); in mce_amd_feature_init() local
590 for (bank = 0; bank < mca_cfg.banks; ++bank) { in mce_amd_feature_init()
592 smca_configure(bank, cpu); in mce_amd_feature_init()
595 address = get_block_address(cpu, address, low, high, bank, block); in mce_amd_feature_init()
609 offset = prepare_threshold_block(bank, block, address, offset, high); in mce_amd_feature_init()
823 return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0; in amd_mce_is_memory_error()
825 return m->bank == 4 && xec == 0x8; in amd_mce_is_memory_error()
828 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) in __log_error() argument
836 m.bank = bank; in __log_error()
854 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); in __log_error()
857 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); in __log_error()
877 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) in _log_error_bank() argument
888 __log_error(bank, status, addr, misc); in _log_error_bank()
904 static void log_error_deferred(unsigned int bank) in log_error_deferred() argument
908 defrd = _log_error_bank(bank, msr_ops.status(bank), in log_error_deferred()
909 msr_ops.addr(bank), 0); in log_error_deferred()
916 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); in log_error_deferred()
924 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), in log_error_deferred()
925 MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); in log_error_deferred()
931 unsigned int bank; in amd_deferred_error_interrupt() local
933 for (bank = 0; bank < mca_cfg.banks; ++bank) in amd_deferred_error_interrupt()
934 log_error_deferred(bank); in amd_deferred_error_interrupt()
937 static void log_error_thresholding(unsigned int bank, u64 misc) in log_error_thresholding() argument
939 _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc); in log_error_thresholding()
957 log_error_thresholding(block->bank, ((u64)high << 32) | low); in log_and_reset_block()
972 unsigned int bank, cpu = smp_processor_id(); in amd_threshold_interrupt() local
974 for (bank = 0; bank < mca_cfg.banks; ++bank) { in amd_threshold_interrupt()
975 if (!(per_cpu(bank_map, cpu) & (1 << bank))) in amd_threshold_interrupt()
978 first_block = per_cpu(threshold_banks, cpu)[bank]->blocks; in amd_threshold_interrupt()
1127 static const char *get_name(unsigned int bank, struct threshold_block *b) in get_name() argument
1132 if (b && bank == 4) in get_name()
1135 return th_names[bank]; in get_name()
1138 bank_type = smca_get_bank_type(bank); in get_name()
1148 if (smca_banks[bank].hwid->count == 1) in get_name()
1153 smca_banks[bank].sysfs_id); in get_name()
1158 unsigned int bank, unsigned int block, in allocate_threshold_blocks() argument
1165 if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) in allocate_threshold_blocks()
1187 b->bank = bank; in allocate_threshold_blocks()
1191 b->interrupt_capable = lvt_interrupt_supported(bank, high); in allocate_threshold_blocks()
1208 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(bank, b)); in allocate_threshold_blocks()
1212 address = get_block_address(cpu, address, low, high, bank, ++block); in allocate_threshold_blocks()
1216 err = allocate_threshold_blocks(cpu, tb, bank, block, address); in allocate_threshold_blocks()
1258 static int threshold_create_bank(unsigned int cpu, unsigned int bank) in threshold_create_bank() argument
1263 const char *name = get_name(bank, NULL); in threshold_create_bank()
1269 if (is_shared_bank(bank)) { in threshold_create_bank()
1280 per_cpu(threshold_banks, cpu)[bank] = b; in threshold_create_bank()
1301 if (is_shared_bank(bank)) { in threshold_create_bank()
1311 err = allocate_threshold_blocks(cpu, b, bank, 0, msr_ops.misc(bank)); in threshold_create_bank()
1315 per_cpu(threshold_banks, cpu)[bank] = b; in threshold_create_bank()
1331 static void deallocate_threshold_block(unsigned int cpu, unsigned int bank) in deallocate_threshold_block() argument
1335 struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; in deallocate_threshold_block()
1359 static void threshold_remove_bank(unsigned int cpu, int bank) in threshold_remove_bank() argument
1364 b = per_cpu(threshold_banks, cpu)[bank]; in threshold_remove_bank()
1371 if (is_shared_bank(bank)) { in threshold_remove_bank()
1374 per_cpu(threshold_banks, cpu)[bank] = NULL; in threshold_remove_bank()
1386 deallocate_threshold_block(cpu, bank); in threshold_remove_bank()
1392 per_cpu(threshold_banks, cpu)[bank] = NULL; in threshold_remove_bank()
1397 unsigned int bank; in mce_threshold_remove_device() local
1399 for (bank = 0; bank < mca_cfg.banks; ++bank) { in mce_threshold_remove_device()
1400 if (!(per_cpu(bank_map, cpu) & (1 << bank))) in mce_threshold_remove_device()
1402 threshold_remove_bank(cpu, bank); in mce_threshold_remove_device()
1412 unsigned int bank; in mce_threshold_create_device() local
1427 for (bank = 0; bank < mca_cfg.banks; ++bank) { in mce_threshold_create_device()
1428 if (!(per_cpu(bank_map, cpu) & (1 << bank))) in mce_threshold_create_device()
1430 err = threshold_create_bank(cpu, bank); in mce_threshold_create_device()