39 	ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);  in clk_pll_enable()
48 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,  in clk_pll_enable()
60 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,  in clk_pll_enable()
69 	return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,  in clk_pll_enable()
79 	regmap_read(pll->clkr.regmap, pll->mode_reg, &val);  in clk_pll_disable()
84 	regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);  in clk_pll_disable()
95 	regmap_read(pll->clkr.regmap, pll->l_reg, &l);  in clk_pll_recalc_rate()
96 	regmap_read(pll->clkr.regmap, pll->m_reg, &m);  in clk_pll_recalc_rate()
97 	regmap_read(pll->clkr.regmap, pll->n_reg, &n);  in clk_pll_recalc_rate()
111 		regmap_read(pll->clkr.regmap, pll->config_reg, &config);  in clk_pll_recalc_rate()
161 	regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);  in clk_pll_set_rate()
167 	regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);  in clk_pll_set_rate()
168 	regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);  in clk_pll_set_rate()
169 	regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);  in clk_pll_set_rate()
170 	regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);  in clk_pll_set_rate()
196 		ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);  in wait_for_pll()
226 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,  in clk_pll_configure()  argument
232 	regmap_write(regmap, pll->l_reg, config->l);  in clk_pll_configure()
233 	regmap_write(regmap, pll->m_reg, config->m);  in clk_pll_configure()
234 	regmap_write(regmap, pll->n_reg, config->n);  in clk_pll_configure()
250 	regmap_update_bits(regmap, pll->config_reg, mask, val);  in clk_pll_configure()
253 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,  in clk_pll_configure_sr()  argument
256 	clk_pll_configure(pll, regmap, config);  in clk_pll_configure_sr()
258 		qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8);  in clk_pll_configure_sr()
262 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,  in clk_pll_configure_sr_hpm_lp()  argument
265 	clk_pll_configure(pll, regmap, config);  in clk_pll_configure_sr_hpm_lp()
267 		qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0);  in clk_pll_configure_sr_hpm_lp()
277 	ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);  in clk_pll_sr2_enable()
282 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,  in clk_pll_sr2_enable()
294 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,  in clk_pll_sr2_enable()
304 	return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,  in clk_pll_sr2_enable()
321 	regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);  in clk_pll_sr2_set_rate()
327 	regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);  in clk_pll_sr2_set_rate()
328 	regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);  in clk_pll_sr2_set_rate()
329 	regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);  in clk_pll_sr2_set_rate()