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Lines Matching refs:reg_data

66 	const struct rockchip_cpuclk_reg_data	*reg_data;  member
93 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; in rockchip_cpuclk_recalc_rate() local
94 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg); in rockchip_cpuclk_recalc_rate()
96 clksel0 >>= reg_data->div_core_shift; in rockchip_cpuclk_recalc_rate()
97 clksel0 &= reg_data->div_core_mask; in rockchip_cpuclk_recalc_rate()
126 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; in rockchip_cpuclk_pre_rate_change() local
152 if (alt_div > reg_data->div_core_mask) { in rockchip_cpuclk_pre_rate_change()
154 __func__, alt_div, reg_data->div_core_mask); in rockchip_cpuclk_pre_rate_change()
155 alt_div = reg_data->div_core_mask; in rockchip_cpuclk_pre_rate_change()
168 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask, in rockchip_cpuclk_pre_rate_change()
169 reg_data->div_core_shift) | in rockchip_cpuclk_pre_rate_change()
170 HIWORD_UPDATE(reg_data->mux_core_alt, in rockchip_cpuclk_pre_rate_change()
171 reg_data->mux_core_mask, in rockchip_cpuclk_pre_rate_change()
172 reg_data->mux_core_shift), in rockchip_cpuclk_pre_rate_change()
173 cpuclk->reg_base + reg_data->core_reg); in rockchip_cpuclk_pre_rate_change()
176 writel(HIWORD_UPDATE(reg_data->mux_core_alt, in rockchip_cpuclk_pre_rate_change()
177 reg_data->mux_core_mask, in rockchip_cpuclk_pre_rate_change()
178 reg_data->mux_core_shift), in rockchip_cpuclk_pre_rate_change()
179 cpuclk->reg_base + reg_data->core_reg); in rockchip_cpuclk_pre_rate_change()
189 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; in rockchip_cpuclk_post_rate_change() local
212 writel(HIWORD_UPDATE(0, reg_data->div_core_mask, in rockchip_cpuclk_post_rate_change()
213 reg_data->div_core_shift) | in rockchip_cpuclk_post_rate_change()
214 HIWORD_UPDATE(reg_data->mux_core_main, in rockchip_cpuclk_post_rate_change()
215 reg_data->mux_core_mask, in rockchip_cpuclk_post_rate_change()
216 reg_data->mux_core_shift), in rockchip_cpuclk_post_rate_change()
217 cpuclk->reg_base + reg_data->core_reg); in rockchip_cpuclk_post_rate_change()
251 const struct rockchip_cpuclk_reg_data *reg_data, in rockchip_clk_register_cpuclk() argument
270 init.parent_names = &parent_names[reg_data->mux_core_main]; in rockchip_clk_register_cpuclk()
284 cpuclk->reg_data = reg_data; in rockchip_clk_register_cpuclk()
288 cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]); in rockchip_clk_register_cpuclk()
291 __func__, reg_data->mux_core_alt); in rockchip_clk_register_cpuclk()
303 clk = __clk_lookup(parent_names[reg_data->mux_core_main]); in rockchip_clk_register_cpuclk()
306 __func__, reg_data->mux_core_main, in rockchip_clk_register_cpuclk()
307 parent_names[reg_data->mux_core_main]); in rockchip_clk_register_cpuclk()