Lines Matching refs:div
35 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
36 (div << SUN9I_CPUS_DIV_SHIFT))
41 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
42 (div << SUN9I_CPUS_PLL4_DIV_SHIFT))
74 u8 div, pre_div = 1; in sun9i_a80_cpus_clk_round() local
83 div = DIV_ROUND_UP(parent_rate, rate); in sun9i_a80_cpus_clk_round()
86 if (parent == SUN9I_CPUS_MUX_PARENT_PLL4 && div > 4) { in sun9i_a80_cpus_clk_round()
88 if (div < 32) { in sun9i_a80_cpus_clk_round()
89 pre_div = div; in sun9i_a80_cpus_clk_round()
90 div = 1; in sun9i_a80_cpus_clk_round()
91 } else if (div < 64) { in sun9i_a80_cpus_clk_round()
92 pre_div = DIV_ROUND_UP(div, 2); in sun9i_a80_cpus_clk_round()
93 div = 2; in sun9i_a80_cpus_clk_round()
94 } else if (div < 96) { in sun9i_a80_cpus_clk_round()
95 pre_div = DIV_ROUND_UP(div, 3); in sun9i_a80_cpus_clk_round()
96 div = 3; in sun9i_a80_cpus_clk_round()
98 pre_div = DIV_ROUND_UP(div, 4); in sun9i_a80_cpus_clk_round()
99 div = 4; in sun9i_a80_cpus_clk_round()
105 *divp = div - 1; in sun9i_a80_cpus_clk_round()
109 return parent_rate / pre_div / div; in sun9i_a80_cpus_clk_round()
156 u8 div, pre_div, parent; in sun9i_a80_cpus_clk_set_rate() local
165 sun9i_a80_cpus_clk_round(rate, &div, &pre_div, parent, parent_rate); in sun9i_a80_cpus_clk_set_rate()
167 reg = SUN9I_CPUS_DIV_SET(reg, div); in sun9i_a80_cpus_clk_set_rate()