17 #define CLK_HW_INIT(_name, _parent, _ops, _flags)			\  argument
20 		.name		= _name,				\
26 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags)		\  argument
29 		.name		= _name,				\
58 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock)		\  argument
65 	.hw.init	 = CLK_HW_INIT(_name, _parent, &zx_pll_ops,	\
73 #define ZX296718_PLL(_name, _parent, _reg, _table)			\  argument
74 ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
81 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags)		\  argument
88 		.hw.init = CLK_HW_INIT(_name,				\
101 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag)		\  argument
106 		.hw.init	= CLK_HW_INIT(_name,			\
119 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag)	\  argument
127 		.hw.init	= CLK_HW_INIT_PARENTS(_name,		\
135 #define MUX(_id, _name, _parent, _reg, _shift, _width)			\  argument
136 MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
143 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table)	\  argument
152 		.hw.init	= CLK_HW_INIT(_name,			\
168 #define AUDIO_DIV(_id, _name, _parent, _reg)				\  argument
172 	.hw.init	= CLK_HW_INIT(_name,				\