Lines Matching refs:ndev
11 static void emu_enable_cores(struct nitrox_device *ndev) in emu_enable_cores() argument
27 nitrox_write_csr(ndev, EMU_AE_ENABLEX(i), emu_ae.value); in emu_enable_cores()
28 nitrox_write_csr(ndev, EMU_SE_ENABLEX(i), emu_se.value); in emu_enable_cores()
36 void nitrox_config_emu_unit(struct nitrox_device *ndev) in nitrox_config_emu_unit() argument
44 emu_enable_cores(ndev); in nitrox_config_emu_unit()
55 nitrox_write_csr(ndev, offset, emu_wd_int.value); in nitrox_config_emu_unit()
57 nitrox_write_csr(ndev, offset, emu_ge_int.value); in nitrox_config_emu_unit()
61 static void reset_pkt_input_ring(struct nitrox_device *ndev, int ring) in reset_pkt_input_ring() argument
70 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
72 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in reset_pkt_input_ring()
77 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
84 nitrox_write_csr(ndev, offset, pkt_in_dbell.value); in reset_pkt_input_ring()
88 pkt_in_cnts.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
89 nitrox_write_csr(ndev, offset, pkt_in_cnts.value); in reset_pkt_input_ring()
93 void enable_pkt_input_ring(struct nitrox_device *ndev, int ring) in enable_pkt_input_ring() argument
100 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in enable_pkt_input_ring()
103 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in enable_pkt_input_ring()
107 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in enable_pkt_input_ring()
115 void nitrox_config_pkt_input_rings(struct nitrox_device *ndev) in nitrox_config_pkt_input_rings() argument
119 for (i = 0; i < ndev->nr_queues; i++) { in nitrox_config_pkt_input_rings()
120 struct nitrox_cmdq *cmdq = &ndev->pkt_cmdqs[i]; in nitrox_config_pkt_input_rings()
124 reset_pkt_input_ring(ndev, i); in nitrox_config_pkt_input_rings()
130 nitrox_write_csr(ndev, NPS_PKT_IN_INSTR_BADDRX(i), cmdq->dma); in nitrox_config_pkt_input_rings()
135 pkt_in_rsize.s.rsize = ndev->qlen; in nitrox_config_pkt_input_rings()
136 nitrox_write_csr(ndev, offset, pkt_in_rsize.value); in nitrox_config_pkt_input_rings()
140 nitrox_write_csr(ndev, offset, 0xffffffff); in nitrox_config_pkt_input_rings()
142 enable_pkt_input_ring(ndev, i); in nitrox_config_pkt_input_rings()
146 static void reset_pkt_solicit_port(struct nitrox_device *ndev, int port) in reset_pkt_solicit_port() argument
154 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_solicit_port()
156 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); in reset_pkt_solicit_port()
161 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_solicit_port()
166 pkt_slc_cnts.value = nitrox_read_csr(ndev, offset); in reset_pkt_solicit_port()
167 nitrox_write_csr(ndev, offset, pkt_slc_cnts.value); in reset_pkt_solicit_port()
171 void enable_pkt_solicit_port(struct nitrox_device *ndev, int port) in enable_pkt_solicit_port() argument
187 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); in enable_pkt_solicit_port()
191 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset); in enable_pkt_solicit_port()
195 static void config_single_pkt_solicit_port(struct nitrox_device *ndev, in config_single_pkt_solicit_port() argument
201 reset_pkt_solicit_port(ndev, port); in config_single_pkt_solicit_port()
207 nitrox_write_csr(ndev, offset, pkt_slc_int.value); in config_single_pkt_solicit_port()
209 enable_pkt_solicit_port(ndev, port); in config_single_pkt_solicit_port()
212 void nitrox_config_pkt_solicit_ports(struct nitrox_device *ndev) in nitrox_config_pkt_solicit_ports() argument
216 for (i = 0; i < ndev->nr_queues; i++) in nitrox_config_pkt_solicit_ports()
217 config_single_pkt_solicit_port(ndev, i); in nitrox_config_pkt_solicit_ports()
226 static void enable_nps_interrupts(struct nitrox_device *ndev) in enable_nps_interrupts() argument
237 nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value); in enable_nps_interrupts()
240 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL)); in enable_nps_interrupts()
241 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL)); in enable_nps_interrupts()
242 nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL)); in enable_nps_interrupts()
244 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL)); in enable_nps_interrupts()
245 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL)); in enable_nps_interrupts()
246 nitrox_write_csr(ndev, NPS_PKT_SLC_ERR_TYPE_ENA_W1S, (~0uLL)); in enable_nps_interrupts()
249 void nitrox_config_nps_unit(struct nitrox_device *ndev) in nitrox_config_nps_unit() argument
254 nitrox_write_csr(ndev, NPS_CORE_CONTROL, 1ULL); in nitrox_config_nps_unit()
260 nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value); in nitrox_config_nps_unit()
262 nitrox_config_pkt_input_rings(ndev); in nitrox_config_nps_unit()
263 nitrox_config_pkt_solicit_ports(ndev); in nitrox_config_nps_unit()
266 enable_nps_interrupts(ndev); in nitrox_config_nps_unit()
269 void nitrox_config_pom_unit(struct nitrox_device *ndev) in nitrox_config_pom_unit() argument
277 nitrox_write_csr(ndev, POM_INT_ENA_W1S, pom_int.value); in nitrox_config_pom_unit()
280 for (i = 0; i < ndev->hw.se_cores; i++) in nitrox_config_pom_unit()
281 nitrox_write_csr(ndev, POM_PERF_CTL, BIT_ULL(i)); in nitrox_config_pom_unit()
288 void nitrox_config_rand_unit(struct nitrox_device *ndev) in nitrox_config_rand_unit() argument
294 efl_rnm_ctl.value = nitrox_read_csr(ndev, offset); in nitrox_config_rand_unit()
297 nitrox_write_csr(ndev, offset, efl_rnm_ctl.value); in nitrox_config_rand_unit()
300 void nitrox_config_efl_unit(struct nitrox_device *ndev) in nitrox_config_efl_unit() argument
314 nitrox_write_csr(ndev, offset, efl_core_int.value); in nitrox_config_efl_unit()
317 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
319 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
323 void nitrox_config_bmi_unit(struct nitrox_device *ndev) in nitrox_config_bmi_unit() argument
331 bmi_ctl.value = nitrox_read_csr(ndev, offset); in nitrox_config_bmi_unit()
335 nitrox_write_csr(ndev, offset, bmi_ctl.value); in nitrox_config_bmi_unit()
343 nitrox_write_csr(ndev, offset, bmi_int_ena.value); in nitrox_config_bmi_unit()
346 void nitrox_config_bmo_unit(struct nitrox_device *ndev) in nitrox_config_bmo_unit() argument
353 bmo_ctl2.value = nitrox_read_csr(ndev, offset); in nitrox_config_bmo_unit()
355 nitrox_write_csr(ndev, offset, bmo_ctl2.value); in nitrox_config_bmo_unit()
358 void invalidate_lbc(struct nitrox_device *ndev) in invalidate_lbc() argument
366 lbc_ctl.value = nitrox_read_csr(ndev, offset); in invalidate_lbc()
368 nitrox_write_csr(ndev, offset, lbc_ctl.value); in invalidate_lbc()
373 lbc_stat.value = nitrox_read_csr(ndev, offset); in invalidate_lbc()
377 void nitrox_config_lbc_unit(struct nitrox_device *ndev) in nitrox_config_lbc_unit() argument
382 invalidate_lbc(ndev); in nitrox_config_lbc_unit()
391 nitrox_write_csr(ndev, offset, lbc_int_ena.value); in nitrox_config_lbc_unit()
394 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
396 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
399 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
401 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()