327 				unsigned int ae_csr, unsigned int csr_val)  in qat_hal_wr_indr_csr()  argument
337 		qat_hal_wr_ae_csr(handle, ae, ae_csr, csr_val);  in qat_hal_wr_indr_csr()
345 				unsigned int ae_csr, unsigned int *csr_val)  in qat_hal_rd_indr_csr()  argument
351 	qat_hal_rd_ae_csr(handle, ae, ae_csr, csr_val);  in qat_hal_rd_indr_csr()
456 	unsigned int csr_val;  in qat_hal_init_esram()  local
462 	csr_val = ADF_CSR_RD(csr_addr, 0);  in qat_hal_init_esram()
463 	if ((csr_val & ESRAM_AUTO_TINIT) && (csr_val & ESRAM_AUTO_TINIT_DONE))  in qat_hal_init_esram()
466 	csr_val = ADF_CSR_RD(csr_addr, 0);  in qat_hal_init_esram()
467 	csr_val |= ESRAM_AUTO_TINIT;  in qat_hal_init_esram()
468 	ADF_CSR_WR(csr_addr, 0, csr_val);  in qat_hal_init_esram()
472 		csr_val = ADF_CSR_RD(csr_addr, 0);  in qat_hal_init_esram()
473 	} while (!(csr_val & ESRAM_AUTO_TINIT_DONE) && times--);  in qat_hal_init_esram()
634 	unsigned int csr_val = 0;  in qat_hal_clear_gpr()  local
639 		qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &csr_val);  in qat_hal_clear_gpr()
640 		csr_val &= ~(1 << MMC_SHARE_CS_BITPOS);  in qat_hal_clear_gpr()
641 		qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val);  in qat_hal_clear_gpr()
642 		qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr_val);  in qat_hal_clear_gpr()
643 		csr_val &= IGNORE_W1C_MASK;  in qat_hal_clear_gpr()
644 		csr_val |= CE_NN_MODE;  in qat_hal_clear_gpr()
645 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val);  in qat_hal_clear_gpr()
761 		unsigned int csr_val = 0;  in qat_hal_init()  local
763 		qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE, &csr_val);  in qat_hal_init()
764 		csr_val |= 0x1;  in qat_hal_init()
765 		qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val);  in qat_hal_init()
883 	unsigned int csr_val = 0, newcsr_val;  in qat_hal_exec_micro_inst()  local
941 	qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &csr_val);  in qat_hal_exec_micro_inst()
942 	newcsr_val = CLR_BIT(csr_val, MMC_SHARE_CS_BITPOS);  in qat_hal_exec_micro_inst()