Lines Matching refs:dmadev
206 static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg) in stm32_dma_read() argument
208 return readl_relaxed(dmadev->base + reg); in stm32_dma_read()
211 static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val) in stm32_dma_write() argument
213 writel_relaxed(val, dmadev->base + reg); in stm32_dma_write()
285 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_irq_status() local
297 dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR); in stm32_dma_irq_status()
299 dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR); in stm32_dma_irq_status()
308 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_irq_clear() local
321 stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr); in stm32_dma_irq_clear()
323 stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr); in stm32_dma_irq_clear()
328 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_disable_chan() local
333 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); in stm32_dma_disable_chan()
337 stm32_dma_write(dmadev, STM32_DMA_SCR(id), dma_scr); in stm32_dma_disable_chan()
340 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); in stm32_dma_disable_chan()
359 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_stop() local
364 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_stop()
366 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_stop()
367 dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_stop()
369 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr); in stm32_dma_stop()
416 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_dump_reg() local
417 u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_dump_reg()
418 u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); in stm32_dma_dump_reg()
419 u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id)); in stm32_dma_dump_reg()
420 u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id)); in stm32_dma_dump_reg()
421 u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id)); in stm32_dma_dump_reg()
422 u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_dump_reg()
436 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_start_transfer() local
462 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
463 stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar); in stm32_dma_start_transfer()
464 stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar); in stm32_dma_start_transfer()
465 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr); in stm32_dma_start_transfer()
466 stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar); in stm32_dma_start_transfer()
467 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr); in stm32_dma_start_transfer()
483 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
492 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_configure_next_sg() local
497 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); in stm32_dma_configure_next_sg()
507 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar); in stm32_dma_configure_next_sg()
509 stm32_dma_read(dmadev, STM32_DMA_SM0AR(id))); in stm32_dma_configure_next_sg()
512 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar); in stm32_dma_configure_next_sg()
514 stm32_dma_read(dmadev, STM32_DMA_SM1AR(id))); in stm32_dma_configure_next_sg()
541 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_chan_irq() local
547 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_chan_irq()
863 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_get_remaining_bytes() local
865 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_get_remaining_bytes()
867 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); in stm32_dma_get_remaining_bytes()
930 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_alloc_chan_resources() local
934 ret = clk_prepare_enable(dmadev->clk); in stm32_dma_alloc_chan_resources()
942 clk_disable_unprepare(dmadev->clk); in stm32_dma_alloc_chan_resources()
950 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_free_chan_resources() local
962 clk_disable_unprepare(dmadev->clk); in stm32_dma_free_chan_resources()
989 struct stm32_dma_device *dmadev = ofdma->of_dma_data; in stm32_dma_of_xlate() local
990 struct device *dev = dmadev->ddev.dev; in stm32_dma_of_xlate()
1011 chan = &dmadev->chan[cfg.channel_id]; in stm32_dma_of_xlate()
1033 struct stm32_dma_device *dmadev; in stm32_dma_probe() local
1045 dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL); in stm32_dma_probe()
1046 if (!dmadev) in stm32_dma_probe()
1049 dd = &dmadev->ddev; in stm32_dma_probe()
1052 dmadev->base = devm_ioremap_resource(&pdev->dev, res); in stm32_dma_probe()
1053 if (IS_ERR(dmadev->base)) in stm32_dma_probe()
1054 return PTR_ERR(dmadev->base); in stm32_dma_probe()
1056 dmadev->clk = devm_clk_get(&pdev->dev, NULL); in stm32_dma_probe()
1057 if (IS_ERR(dmadev->clk)) { in stm32_dma_probe()
1059 return PTR_ERR(dmadev->clk); in stm32_dma_probe()
1062 dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node, in stm32_dma_probe()
1065 dmadev->rst = devm_reset_control_get(&pdev->dev, NULL); in stm32_dma_probe()
1066 if (!IS_ERR(dmadev->rst)) { in stm32_dma_probe()
1067 reset_control_assert(dmadev->rst); in stm32_dma_probe()
1069 reset_control_deassert(dmadev->rst); in stm32_dma_probe()
1096 if (dmadev->mem2mem) { in stm32_dma_probe()
1103 chan = &dmadev->chan[i]; in stm32_dma_probe()
1114 chan = &dmadev->chan[i]; in stm32_dma_probe()
1134 stm32_dma_of_xlate, dmadev); in stm32_dma_probe()
1141 platform_set_drvdata(pdev, dmadev); in stm32_dma_probe()