Lines Matching refs:gpu_addr
232 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_emit_ib()
233 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
483 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in cik_sdma_gfx_resume()
485 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); in cik_sdma_gfx_resume()
489 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in cik_sdma_gfx_resume()
490 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); in cik_sdma_gfx_resume()
627 u64 gpu_addr; in cik_sdma_ring_test_ring() local
635 gpu_addr = adev->wb.gpu_addr + (index * 4); in cik_sdma_ring_test_ring()
646 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
647 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
686 u64 gpu_addr; in cik_sdma_ring_test_ib() local
695 gpu_addr = adev->wb.gpu_addr + (index * 4); in cik_sdma_ring_test_ib()
707 ib.ptr[1] = lower_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
708 ib.ptr[2] = upper_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
859 uint64_t addr = ring->fence_drv.gpu_addr; in cik_sdma_ring_emit_pipeline_sync()